Re: Place Via in conductive shape
Hello, The comments about Net0 are correct. We do not allow multiple Net0 objects to connect to each other which would be bad since unused pins in a part are Net0 and you would not want to connect...
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Re: Header vs. Socket - Naming
Homer Naming Conventions in Library creation tend to be personal preference for some users. I myself use "skt" as the prefix to match the "hdr" prefix. If you have not yet downloaded the FREE Starter...
View ArticleReport of libraries used in a design
Is there an easy way (report or otherwise) to list all libraries used in a design?
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Re: Making PCB with concurrent design enabled xpedition project
Hi,The schematic was drawn by several people in xPedition VX.1 . Since we don't have xtream user licenses we cannot make the PCB concurrently. Now our layout engineer tries to make a PCB from the...
View ArticleRe: CHS Licensing Error
Hi Suhas, The warning "Interactive Service Detection" does not appear when I install the license file correctly. So I guess there might be some incorrect procedure for your license installation but...
View ArticleRe: Report of libraries used in a design
I dont think the library name will be attached to the decal once it is used in the layout ( unlike schematic), so we cannot extract the list of libraries used in the design.
View ArticleRe: Report of libraries used in a design
I'm fine with this in schematic as opposed to layout. Is there a way of doing this in schematic?
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Re: Making PCB with concurrent design enabled xpedition project
The 'remote development flow' makes me think that the PCB has been previously undocked (or exported in xDM for remote development).This is used when the PCB layout team is not part of the same...
View ArticleRe: Report of libraries used in a design
AFAIK In DxDesigner there is no direct option to export this data, but i guess we can get this data by using scripts. In PADS Logic, the same rule applies as PADS Layout
View ArticleRe: Server setup of Valor Tool
Hello, While running on a virtual machine is not specifially supported, many customers run their vNPI servers in a virtual environment. The latest version of vNPI is 9.5.1. It is supported on Windows...
View ArticleRe: Missing Start Menu application links - Pads 9.5
Hello, This kind of question is best answered by one of our support team. Please open a service request and someone will assist you. Regards,Joy
View ArticleRe: Logic part type defined as PWR, allows GND net to connect to it?
What really happened is that the engineer connected the wrong net to the wrong pin on a part. No different than if he connected an input net to a part output pin. Or a Load to a Source. Logic Pin...
View ArticleRe: Report of libraries used in a design
try this: report = Application.DefaultFilePath & "\Parts in libraries.rep"Open report For Output As #1Print #1, "Library locations for PartTypes in " & ActiveDocument.FullNamePrint #1For Each...
View ArticleObtaining Hierarchical Netlist with Calibre PEX
Hello, I would like to perform hierarchical extraction with Calibre. For that, I select the following options: Extraction mode: xRCExtraction type: "hierarchical" "C + CC"Format: spectre or hspice...
View ArticleRe: QuestaSim pli simulation cannot find symbols
Hello Yanxiang, At this time, our community site is not setup for QuestaSim simulation discussions/questions, sorry.You might open a new service request for this on our SupportNet site,...
View ArticleRe: Obtaining Hierarchical Netlist with Calibre PEX
Hello Can, I don't have xRC experience to be of much help on this question. If it's still an issue for you and we're not getting any responses from other user's you might consider opening a service...
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Re: Pads Layout - Assembly Variant - bug in library name?
Hi We also have problems with the substitution of components in Pads Logic. We are trying to sustitute different components with different values from the same library in Pads Logic 9.5. When creating...
View ArticleRe: Pads Layout - Assembly Variant - bug in library name?
If you feel it is a bug you can raise a service request and inform mentor. In the mean time i can suggest a workaround, you can place both the parts in the schematic and in the layout just overlap the...
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