Using OneDrive for \PADS Projects\ ?
HiHas anyone experience with placing the \PADS Projects\ directory on a OneDrive location?I was wondering if there may be some compatibility issues because OneDrive is constantly synchronizing from the...
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Re: COVER FREE AREA
Hi Vernon, thanks for your explanation.I have tried this line $Lnew create layer 3$Lnew create polygon cellname 3 (6567500 8367500) (6567500 -8367500) (-6567500 8367500) (-6567500 -8367500) (-2347500...
View ArticleFind and Replace with Wildcard or Regular Expression fails for Properties in...
Hi, I'am using X-ENTP VX.2. When I want to replace pin properties in symbol editor with wildcards it is not working for me. It is working for names only. Example: Find what: ABC0*Replace with:...
View ArticleRe: Efficient method to update Capital Library connector wire fits cavity...
We have a large amount of unique connectors. I am not sure if the copy component details capability is efficient enough for what we are looking for. Is it possible to create a plugin using the API to...
View ArticleRe: Find and Replace with Wildcard or Regular Expression fails for Properties...
It appears to be a bug. Depending on what you are trying to do there may be an alternative way of doing this. Are the property names/values unique?
View ArticleRe: Find and Replace with Wildcard or Regular Expression fails for Properties...
Yes, they are unique. I have tons of pins with the same prefix in both, pin name and number, and I want to copy them all and replace the prefix. I can export pins, replace pin number in a spreadsheet...
View ArticleRe: Find and Replace with Wildcard or Regular Expression fails for Properties...
The simplest solution would be to use Add Properties. Select all the pins you want to change and reset the values with Add Properties configured to do so, in your example you'd set the Type to Pin and...
View ArticleRe: Efficient method to update Capital Library connector wire fits cavity...
Robert - we make this easier using wire groups which allow you to specify a collection of wire specifications that will be similar for the 'wire fits' relationship. However, you still need to apply...
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Re: COVER FREE AREA
Hi Luciano, It sounds like you want a layer that occupies all the space in your design not occupied by the current layers/cells in the design. I would do a NOT operation in this case ($L NOT). Here's...
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Manage Central Library in xDxDesigner with Integrated flow
Hello Everyone, I recently switched to integrated flow with the xDxDesigner and Pads Layout (VX1.1). The integrated flow indeed provides lots of convenienceby centrally manage all symbols, decals and...
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PADS 3D, custom attribute in silkscreen layer
Hi,I tried the PADS 3D function with PADS VX.2.I have a part with an attribute: "Part Number" and it value is on the silkscreen layer.Now the PADS 3D view doesn't show this attribute value.If I change...
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Re: Hyperlynx differential impedance calculation mistake
Hello!I have noticed that you selected, in Saturn PCB, ”Edge Coupled Ext” for the Differential Layer option. This would be valid if the differential pair was on an external layer.If you select ”Edge...
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Re: Hyperlynx differential impedance calculation mistake
Dear fiend Mircea Slanina, thank you for your attention and response !You are right, my Saturn stackup model was wrong. I looked on this as on Microstip, because it is Flexible PCB where the flexible...
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Hyperlynx differential impedance calculation mistake
!Hi,I'm simulating an exported from Altium designer 16.1 Rigid Flex PCB board, which contains suppose to be 100 ohm diff pairs . The Hyperlink calculates its Zdiff as 82 ohm for some reason .1. The...
View ArticleLinking Different Standard Reference Schematic to Single Schematic
Hello All , We are using PADS 9.2 and we want to link different schematic to single schematic . Is it possible ? Suppose we have a standard reference schematic for every circuit diagram with the...
View ArticleClearance between Signals
Hello All , I have a doubt regarding clearance between different single ended signals . Right now we are keeping the same clearance between the traces as that of the signal trace width . For Example ....
View ArticleRe: Clearance between Signals
Hello Parth, I've moved your question to the HyperLynx SI community for a quicker response. Best regards, Cathy
View ArticleHow do I "overlap" vias with testpoints.
The testpoints are only on the bottom side. The company does not want to use vias for testpoints, nor do they want to have a trace go from a via to a test point (antennas). I have been instructed to...
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Re: How do I "overlap" vias with testpoints.
I haven't tried any of this, but it is an idea that I think may resolve your problem.1st Define your test point pad as an oval shape with an offset origin (similar to sketch included)2nd Then on your...
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Re: COVER FREE AREA
Hi Matthew thanks for your supportUnfortunately doesn't work correctly how I need in my gds file: In my hierarchy.Layer 997 is like your 3Layer 998 is like your 4Layer 999 is like your 50 In my...
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Re: COVER FREE AREA
Hey Luciano, Without knowing exactly what you want, I tried to come up with something that demonstrates a number of options for you. Run this script in DESIGNrev to see the output. I think it will be...
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Re: How to export a complete net from layout which was found by Calibre LVS...
Hi,Sorry for not getting back to you. I have not personally tried to do this sort of thing, so I'd be guessing. Perhaps it's possible with an annotated GDS. There are a few how to videos on those as...
View ArticleRe: How do I "overlap" vias with testpoints.
You can allow vias under the pad in the editor control but you should create a unique pad in the padstackeditor for testpoints just in case same pad is used on SMD components to avoid accidental vias...
View ArticleRe: Database for DxDatabook
We use a defined workflow for part creation. Everyone has access to the database but noone is allowed to alter the database alone.
View ArticleRe: Manage Central Library in xDxDesigner with Integrated flow
Hi Liang,I can help with a couple of your questions. 2 and 3 are maybe's... 1.) Open 2 layouts, layout 1 should have the decal you want to move to your central library, layout 2 should be tied to a...
View ArticleRe: COVER FREE AREA
Hi Mattew, I'll try explain You better. This is my scrpt I need that on layer 999.1 will be present the NOT of layer 997 only on cell MPW_SL...
View ArticleRe: Load Color Scheme in DxDesigner
2: Example script showing how to run sch2pdf: https://communities.mentor.com/message/15689#comment-15689 3: Example of how to load color schemes: Loading a DxDesigner color scheme file
View ArticleRe: Manage Central Library in xDxDesigner with Integrated flow
Hello Travis,Thanks a lot for sharing the trick! Regarding your reply to my first question, that's exact what I figured out as a walk around: work reversely frompad layout instead of from the central...
View ArticleRe: Capital launcher question
Let me chime in here that the users at Cirrus all work in both Logic and HarnessXC. We would love to be able to access one from the other. And it appears that the Trace command in v2015 helps in that...
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How do I add properties to a wire in Vesys Design
I'm trying to add color and wire size, and then have it displayed on my schematic. However, when I put information into the respective properties in the properties dialogue, I'm unable to save the...
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