Re: Macro black boxing without extraction
Hi Arjun, I think the answer depends on the specific situation. EXCLUDE CELL and LVS BOX and LVS FILTER can be applied separately to the layout and the source and they may be needed in different ways...
View ArticleRe: Macro black boxing without extraction
HI Chris, Actually my results are as mentioned below. Layout Source Component Type ------ ------ -------------- Ports: 2 227...
View ArticleRe: Macro black boxing without extraction
LVS FILTER statements in the rule file, should cause those source netlist devices to be ignored during the LVS run.
View Articlepycell file in pyxis
Hi everyone,I have just tried to install iPDK from TSMC for Pyxis 10.1. The installation requires $MGC_HOME/etc/appl/pycell, which I cannot (the directory $MGC_HOME/etc/appl/ is empty). Is there any...
View ArticleDA_IC Segmentation Fault / Violation
Hi All, I am using ICStudio 2008.1 (yes I realize this is outdated, we have some existing designs and we do not want to make tool changes in the middle of them) running on Linux 64bit. When using da_ic...
View ArticleRe: DA_IC Segmentation Fault / Violation
One thought is to locate the "Calibre Administrator's Guide" for the version you are using and check to see if the operating system you are using is newer than those that were qualified back in 2008....
View ArticleUsing Calibre to generate Verilog netlist and SPEF file PrimeTime
Hi, I now have a layout containing stadard cells in Cadence Virtuoso, and want to generate a Verilog netlist of this layout and an SPEF file to excute STA for this design using PrimeTime. Can Calibre...
View ArticleRe: Using Calibre to generate Verilog netlist and SPEF file PrimeTime
I don't know about Verilog -- shouldn't that come from Virtuoso's stream out? -- but if you are using Calibre xRC or Calibre xACT you can get not just a SPEF netlist, but one set up for PrimeTime. In...
View ArticleRe: Using Calibre to generate Verilog netlist and SPEF file PrimeTime
Thanks,Still some questions: 1. Should that the SPEF extraction for a standard cell based digital circuit be excuted using gate-level extraction?2. Can the STA result based on SPEF from Calibre be...
View ArticleRe: Using Calibre to generate Verilog netlist and SPEF file PrimeTime
1. If you are extracting only the standard cell, you should probably do flat extraction. If you are doing a design with standard cells, gate-level is a better fit -- but you will need models to...
View ArticleRe: How to add placement restriction keepout in PCB Decal at Library Level ?
It works on my system but not on yours so i think you'll need to submit a Service Request with Mentor to figure this one out.
View ArticleRe: Unwanted lines found in Inner Layers for Translated Components
Are they a manufacturing issue or just ugly? You might need to recreate the part by hand instead of using the translation.
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Re: How to add placement restriction keepout in PCB Decal at Library Level ?
Hello, You can add Placement Keepout with height restrictions in Decal. Regards, Yan
View ArticleRe: Text linestyle direction
Peter - thanks for your question. This member Resources community is for questions related to the communities in general (like suggestions, feedback, etc) and not product related questions. I would...
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PADS Layout 9.5 NC drill with partial via.
Hi, How do I generate NC drill with partial via's data? I have partial via in my design but in the NC drill option, the Partial Vias check box is grayed out. What am I missing ? attachment is the menu...
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Re: PADS Layout 9.5 NC drill with partial via.
Bobby, You need to setup Drill Pairs in Setup > Drill Pairs where you indicate beginning and end layer. Make sure you also create partial vias corresponding to the Drill Pairs Regards, Yan
View ArticleRe: Unwanted lines found in Inner Layers for Translated Components
Hi , This are not any manufacturer issues . Unwanted lines are just seen in layout design . Well creating a new PCB Decal will be the last option left but just wanted to know the reason behind these...
View ArticleRe: How to add placement restriction keepout in PCB Decal at Library Level ?
Hi , Can you please let me know the PADS version you are using ? I am using PADS 9.2 . Does it work on PADS on 9.2 ?
View ArticleRe: How to add placement restriction keepout in PCB Decal at Library Level ?
I Am using the latest version. This feature was in Pads 9.5 and up
View ArticleRe: Unwanted lines found in Inner Layers for Translated Components
HI disable all the layer first and then enable the layers one by one. you can find the unwanted lines.(or else click the lines and check which layer it is present)
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