Re: need help with v2lvs utility
Thanks Jean!! Yes I think it would be better for us to follow this approach. Thank you all for sharing the information. Regards,N
View Articleuser guide for pyxis v10.2
Somebody knows where I can fin a start guide for pyxis v10.2? i just installed it
View ArticleClik here to view.
Re: . I try to verify the layout by running DRC and LVS checks. I bring up...
If you go to line 822 in the rule file, is that in the middle of some DRC rule check that uses NET AREA RATIO? Right after a NET AREA RATIO statement, it is allowed to have an "expression" that...
View Articlecroswell violations in IC design
As the title above, what is crosswell violation in a ic design. Kindly need some references or notes regarding it, thanks.
View ArticleRe: croswell violations in IC design
Hi Thana- To the best of my knowledge, this is not a predefined Calibre check -- you'll need to ask the group who provided your rules what they mean by it. A quick Google search showed there are a...
View ArticleRe: croswell violations in IC design
Hi Samantha, Thank you for the reply. Actually i'm refering it to IC Compiler (SOC_design). A power well triangle is applied in every chip design which is the boundaries for different type of cell. For...
View ArticleRe: croswell violations in IC design
Hi Thana- IC Compiler is a Synopsys product. It is true that Calibre Interactive can be integrated with it, but if the error is coming from IC Compiler it could be one of its checks. If this is...
View ArticleRe: croswell violations in IC design
Hi Samantha, Thank you for the concern. I will try to do things like you said and maybe if i can get a solution i will post it here. Regards,Thana
View ArticleRegister Now! Mentor Graphics User Conference 2013 - April 25 - San Jose
Mentor Graphics User Conference - April 25, 2013 - San Jose. Talk with experts on IC Layout. Special session from Chenming Hu, creator of the 3D transistor FinFET. Lunch & network reception...
View ArticleCould not esatblish connection with calibre interactive on socket localhost 7000
Dear All, While running DRC i am getting following error:-Could not esatblish connection with calibre interactive on socket localhost 7000\ And I am NOT able to RVE results.How this can be fixed ? Kind...
View ArticleRe: Could not esatblish connection with calibre interactive on socket...
It may be license issue. Execute echo $MGLS_LICENSE_FILE at your linux terminal and see if it's connected to the license server.
View Articlecalibredrv
How can I dump the cell tree from calibre DesignRev? Its already exists in the tool, How do I to save it to a file.
View ArticleRe: calibredrv
Hi Dave Have a look to calibre documentation: Calibre DESIGNrev Reference Manual -->Example Script --> Creating a Batch Script Threre is an exmaple to get tree from a gds2 file. Regards
View ArticleRe: Could not esatblish connection with calibre interactive on socket...
Hi When you start calibre RVE go to "Setup --> Design Tools "Check your "layout Design tool"Verify "Connection" and "socket number" From your layout tool set the socket number :For Calibre...
View ArticleMacro black boxing without extraction
Hi, I have a macro cell placed in the toplevel. The macro level routes are shorting with the top level routes. I need an option to avoid the extraction of that particular macro. LVS BOX is not working...
View ArticleRe: Macro black boxing without extraction
Hi Arjun, If you really want to ignore the macro completely you could use the following statement in your rule file: EXCLUDE CELL mycellname It takes effect during the connectivity extraction phase of...
View ArticleRe: Macro black boxing without extraction
Hi Chris, A couple of doubts. * Is BOX and EXCLUDE options mutually exclusive?* If we specify some cells in EXCLUDE, is it really required to use LVS FILTER <mycellname> OPEN to those cells?...
View Article