Hi Samantha,
Thank you for the reply. Actually i'm refering it to IC Compiler (SOC_design). A power well triangle is applied in every chip design which is the boundaries for different type of cell. For example, cell that will turn off first when you shut down your system or cell that will be always in on state. Isolation of a signal is needed if the signal was driven from a partition with a different power plane to the load of the signal. So i'm actually looking for a proper documentation on this cross well violation and some solutions if you encounter one.
Thanks.
