Hi,
We are finishing up our first project in xDX designer and PADS Layout VX.1. We formerly used PCAD and typically would generate a fab drawing like below:
Where can I create a template to use like Schematic capture? Do I have to export this information to Autocad or the like?
What does Mentor suggest is the case size used for the naming of schematic symbols? Should they be in upper or lower case? In View draw we always used lower case. I'm starting to see symbol names in upper case (CAPS) letters. I could not find the document which says we should use lower case letters, upper case letters or a combination of both. I've seen that document some place but can't put my finger on it. Does this matter anymore?
Thanks for your help.
Hi
On my last workplace I used parallelism rules set up in CES to check for crosstalk risks when using the DRC check in PCB expedition.
At my new workplace I can set up the rules but there is no such check in the online or batch DRC check. My guess is there may be a license missing, so my question is: what is needed to get this function?
/Johan
If you've ever found yourself asking this question, you may want to check out our new PADS blog series, which is devoted to exploring the benefits of a constraints-driven PCB design flow. Steve Hughes explains in the first post the importance of rule definition and management. Read it on the PADS blog!
Steve also poses an interesting set of questions at the end:
Let us know what you think, and stay tuned for the second and third installments of the blog series.
I keep my PADS designs (and an occasional DxD design) archived in Subversion (TortoiseSVN for Windows). I've heard people compare it to GIT.
A few ideas to get you started:
Once you create your titleblock in Layout (a DXF import might be helpful) you can save it to a library as a '2D Lines' object.
I keep copies of my standard notes and stackup for 2, 4, 6 layer designs in the library.
You can generate a Gerber file or a PDF file for your output.
I created a template design that I 'usually' start with. Don't forget to make it read-only!
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Mixed case symbol names are supported if you area talking about the file name. Spaces and many special characters are not allowed.
For the PADS flow, properties and property values that are synchronized with PADS Layout are required to be UPPER case. If mixed case is used, ViewPCB will convert the properties to Uppercase.
Hi Gary,
So I could name my transistor symbol “BJT_NPN” or “bjt_npn”, in my library and either way will work? I’m used to naming my symbols in lower case. It’s good to know.
Thanks
A couple of years ago we bought BluePrint-PCB to do our PCB documentation.
It works pretty good. Especially if you need to handle multiple pages with title blocks and revisions on every page.
It reads the PADS ASCII file and is very quick when updating existing documentation.
regards
Klaus
I find it MUCH easier to export to a 2D CAD editor. Especially on boards that also need 3D assembly models. PADS just doesn't have the documentation power of a documentation program.
It appears that with the 7.9.x releases, netlister is now attempting to update the PKG_TYPE property. Our config file has setups to replace pin name specific decals (ex:SOT-23_EBC) with generic decals (ex: SOT-23N). Prior releases made this substitution on the output, and did NOT updated the property. This update is making the users have to remove the update/instance and re-validate the schematic (painful process!). So my question to the community is there a way to stop netlister from updating this property?
Hi Simon (I'm assuming you will be the one looking into this),
I've completed a plugin that reads net names from a csv file and compares the names to the selected nets in a design. If the names match, then a circuit id property is assigned to the net.
The plugin is intended to run on a buildlist.
The problem is that that the plugin seems to run continuously. When the plugin starts, it requests the csv file to use, and then starts running through the design....and doesn't seem to want to stop. I've let it run for about an hour at a time before manually shutting it down.
I was hoping you could take a look at the main routine below and see if there's anything you notice that could be causing this, or if it's simply due to the amount of data that's being handled.
try{
br = new BufferedReader(new FileReader(mapFile));
while ((line = br.readLine()) != null){
String[] items = line.split(cvsSplitBy);
circuitID.put(items[0],items[1]);
for (IXBuildList buildlist : ixac.getSelectedObjects(IXBuildList.class)){
for(IXDesign b_list : buildlist.getDesigns()){
for(IXNet net: b_list.getConnectivity().getNets()){
String netName = net.getAttribute("name");
String netShared = net.getAttribute("SharedObjectRevision");
if(netShared !=null || !netShared.isEmpty()){
if(items[0].compareToIgnoreCase(netName)==0){
// net.getAttributeSetter().addProperty("Circuit ID", items[1]);
cons.println(items[0]);
}
}
if(items[0].compareToIgnoreCase(netName)==0){
// net.getAttributeSetter().addProperty("Circuit ID", items[1]);
cons.println(items[0]);
}
}
}
}
}
}catch(IOException ex){
Logger.getLogger(Set_Circuit_ID.class.getName()).log(Level.SEVERE,null, ex);
Hi John,
I can't see anything obviously wrong with the code. However, the algorithm you are using is going to be VERY slow. For each line in the CSV you are looping through every net in every design in the buildlist. Assuming you have tens of designs and hundreds of nets, that is a lot of data to process (over and over again).
A better approach would be to read the CSV file data into some sort of datamodel in memory. You can then process the buildist designs and nets once. For each shared net, you would lookup the data in the CSV datamodel that you have previously loaded.
Simon
If you connect either power or ground pins to different supplies the packager will assign the gate to a different package as it sees it as a new part with different power requirements. If you have also assigned the same Reference Designator or Pkg Group you will get a packaging error indicating the conflict. Personally I prefer to use implicit pins for logic gates and override with Supply Rename if necessary. For Op-Amps you need to carefully manage the Pkg Groups to ensure each part is powered, there is no automatic check to ensure for every three un-powered symbols (in a four slot device) that you have a corresponding powered symbol. In this case I prefer to use a single symbol with power for all slots (only one symbol in the library), it requires more wiring in the schematic but ensures that all devices are powered.
You need to distinguish between the symbol name in the symbol definition file and the file on disk, in general (though not always the case) the file on disk is saved as lower case to ensure compatibility between Linux and Windows and if you have mixed platforms then using spaces in names can be problematic.
Thank you Simon. I suspected that may be the case.
I haven't written code in a long time, so I'm fumbling my way through this trying to get back up-to-speed.
I will definitely reconsider my algorithm and take your approach.
Thanks again!
Hi Robert,
Some times a picture is worth a thousand words.
If the only reason symbol names are in lower case is to ensure compatibility between Linux and Windows than everything is right with the world. I was used to seeing these names in lower case so I just wanted to question it just to be safe. I had this fear that something would be affected somewhere else due to the symbol names being in upper case.
Thanks
.
I have symbol names that are a mix of upper and lower case. I also use DxDesigner automation. The ChangeComponent method has a problem with symbols with upper case letters in the name. It works fine with symbol names that are all lower case. This is a known bug that was supposed to have been fixed by now but it appears that it is still in EE7.9.5 update 32. Or maybe they fixed it and it has come back again. This is the first problem that I have had with mixed case symbol names. I also seem to remember that if you decide to rename your symbols from CAP_POL to cap_pol later after CAP_POL has been used a bit that this may not go totally smooth either. I can't remember what the issue was with that. Maybe Gary or Robert knows what I'm talking about.
Hello Folks,
I am stuck in a quiet simple and basic example.
I would like to simulate a clock that is a differential clock.
The topology is quiet simple, as it is visible in this picture. (Be aware that the signal goes from right to left)
The outputs of IC28 are defined as signal and inverted signal.
Now the question itself. If I start a simulation the stimulus of one of the ports is oscillating, while the other is not.
I started a simulation with ezwave.
As is visible in this picture one signal is flat the other oscillates as expected.
The end result is a flawed simulation, as the lower signal is subtracting one oscillating waveform from a flat waveform and the result is useless.
Does anyone know how to make sure that both outputs oscillate one in opposite phase of the other?
It must be very simple, but I am missing the obvious.
Thanks
Matija