That sounds like the single-layer form of Net Area Ratio to me. (Documented in the SVRF manual, svrf_ur.pdf.) Does this work for you, or is there something not quite right?
If you need something a bit more customized, there might be some code you can leverage from the Solutions for Physical Verification manual, particularly the examples using DFM. Look for calbr_solns_pv_user.pdf in your mgcdocs directory.
Thnaks Robert.
What about if i want to show nothing instead 0? If i enter nothing in my Access table why DxDatabook fill the field with 0? 0 is not nothing. This happen only for field marked as "Show Unit for IEC62"
Same for us, too. We use IEC62 format and have symbols that are used in mutiple parts database entries. Some parts have a value and some not. A visible "0" at the parts with no value is not nice.
It is a limitation of how real numbers are handled as far as I understand the problem.
Currently when I want to open DxDesigner, I run a exectuable (of batch file) that copies some files from a network drive to my local drive and then invokes viewdraw.exe. For a couple of reasons, it would make more sense to just run a batchfile or executable via the Run at Startup option in DX. Unfourtunally this doesn't work, DX complains about the .bat or .exe extension not being registered.
How should I get this to work?
Thank you in advance!
Mark
Hi,
I merged 5 different gds files into a unique layout like the image for example
I would like to know if it's possible to cover all free area around chips with a specific layer, using a command like "create polygon" or something like this on tcl script running calibredrv
Many thanks in advance
Best Regards
Luciano
Clear Matthew
Many thanks again
regards
Luciano
Which version you are using ?
If EE7.9.3 onwards; I suggest to use iCDBProjectBackup utility...
Hello Robert,
Where would I find this info within the project, checked settings, nothing like this there. I am having the same problem, pcb: Error 5709: Could not open schematic Schematic1.
Thanks
Need some help, using PADS VX1.2, trying to compile my schematic and getting this error.
Already tried the symbol library fix, and that didn't seem to work.
Here is the full error list,
Finished C:\MentorGraphics\PADSVX.1.2\SDD_HOME\common\win32\bin\pcbui.exe
Started C:\MentorGraphics\PADSVX.1.2\SDD_HOME\common\win32\bin\pcbui.exe -p "C:\Users\fr821d\Desktop\New Mem IO\Memory IO\Memory IO.prj" Board1 -hideresultstab
Finished C:\MentorGraphics\PADSVX.1.2\SDD_HOME\common\win32\bin\pcbui.exe
Started C:\MentorGraphics\PADSVX.1.2\SDD_HOME\common\win32\bin\pcbui.exe -p "C:\Users\fr821d\Desktop\New Mem IO\Memory IO\Memory IO.prj" Board1 -hideresultstab
C:\MentorGraphics\PADSVX.1.2\SDD_HOME\common\win32\bin\pcbfwd.exe "Schematic1" -p "C:\Users\fr821d\Desktop\New Mem IO\Memory IO\Memory IO.prj" -config C:\MentorGraphics\PADSVX.1.2\SDD_HOME/standard/pads100.cfg C:\Users\fr821d\Desktop\New Mem IO\Memory IO\Memory IO.prj
Note 5996: Using Config File C:\MentorGraphics\PADSVX.1.2\SDD_HOME\standard\pads100.cfg
Warning 5720: Check LogFiles/Schematic1.err for VIEWBASE messages
Error 5709: Could not open schematic Schematic1
Note 5626: Summary of LogFiles/pcberr.log
Status 0, Notes 1, Warnings 1
Errors 1, Failures 0, Fatals 0, Internals 0
PCB Forward Interface - V6.1; xDX Designer PADS VX.1.2 (697990)
c Copyright 2015 Mentor Graphics Corporation. All Rights Reserved.
PCBASG netlisting is completed with errors. Check pcberr.log file for notes and information.
Hi Luciano,
That's very doable. I've drawn large chip-surrounding polygons required by foundries before in just such a fashion. Here's some code that will do the trick. This would be typed into the terminal from which you launched your CalibreDRV session at the DRV TCL prompt.
set cwb [ find objects -class cwbWorkBench ]
set L [ $cwb cget -_layout ]
$L create polygon TOPCELL 0 0 0 2u 2u
CalibreDRV uses object-oriented TCL, which you don't run into everywhere. Let's break the code down:
Hello Kjell,
Currently we can't simulate this case in HyperLynx. In IBIS there is no support for simulating drive to 3-state or 3-state to drive modes. Additional V-t tables in the IBIS model are needed to know how to transition to/from 3-state to driving high or low. It is not too difficult to generate this data, the problem is that IBIS does not have a place to have it. The simulator also needs to have transitions implemented between the 3-state and driven modes.
This is a good idea and I encourage you to post it to our HyperLynx Ideas site:
https://communities.mentor.com/community/ideas/hyperlynx-ideas
The problem with odb++ is the pin map,
In odb++ file,
# CMP 1
CMP 85 11.8799213 -5.1072834 180 N U423 TPS7A8300RGRR ;0=1,1=0.0394
TOP 0 11.9478347 -5.1466535 180 N 132 6 U423-1
TOP 1 11.9478347 -5.1269684 180 N 0 1552 U423-2
while import into Hyperlynx, it recognize as component U423, pin as U423-1 instead of U423 pin 1. Although I can use text edit to delete U423-, but it is not an ideal solution.
I'm having this exact same problem. Behavior is the same whether I invoke from toolbar icon or from menu Tools\Package.
Please advise.
awesome.. thank you!
お世話になっております。
2010年5月に購入したL-Edit（Ver15.2）をPCにインストールしたのですが
PCにはUSBKeyを刺したで立ち上げようとすると、以下の内容のメッセージが
表示され、動作しません。
どのような手続きをすればよろしいでしょうか？
Setup - Settings - Symbol Libraries. The first entry should be the name of the project with a .
It is probably caused by the spaces in the names of the project file and path. Try replacing these to see if the issue is resolved.
Thanks Robert,
Tried this already, didn't work. Also, I have many projects with spaces in the project and path and have never not had them compile. I have read mentor software doesn't like that but it has never been an issue for me.
Thanks Robert,
I was referring to how to view this information,
SECTION DesignInfo
LIST IndependentLibraries
VALUE "DIR [W] . (PSDB)"
I downloaded crimson editor and was able to verify the information above.