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Re: Hyperlynx IBIS model issue (DDR simulation)

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hai

what is the controller u are using and what is the ddr chip u are using ?it seems like you have selected two different models for the similar nets  for eg DQS Net you have used 2 different model check the mapping properly ,have u choose automatic mapping map proper group of signals like all data to data group address cmd cntrl to the respective group and data skew to DQS group clock to clock group 


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