Hello everyone,
I am attempting to adjust the B size border from the default 2x4 sections to be 5x10 sections. I have been completely unsuccessful and could use some guidance. As it is the borders in PADS VX 1.1 seem to be scaled very large compared to the actual paper size, the B size block measures 2" x 6" when I print it.
Thanks
Component의 pin을 Buried 하고자 합니다.
아래와 같이 Script 실행 하면 Pin의 TieLegType은 변경 되지만 Plane shape은 변화가 없고 이전 상태로 보입니다.
하여 plane shape을 refresh 하고 싶은데 어떻게 하면 되는지요?
Set Compscoll = pcbDoc.Components
For Each ocomp In Compscoll
Set pinscoll = ocomp.pins
For Each opin In pinscoll
opin.TieLegType = 4 'epcbTieLegBuried
Next
Next
DxDesigner or Logic?
DxDesigner for PADS Integrated Flow.
DxDesigner for Expedition. Thank you!
Hi There,
I have installed mentor Expedition and it crashes as soon as I open it with fault module KERNELBASE.dll
I googled a lot and it seems like it is such a nasty problem and I have already done sfc /scannow and came up with 100% verification
any ideas?
Cheers,
-MR
Hi Yan
Thanks for the feed-back .
My feeling is that an i5 with nvidia graphics
Will not be powerful enough to do 3D placement and
Routing .
We are looking at Intel i7-4790k Devils Canyon
with 16G ram DDR3-2400.
and a 240G Solid state drive
And a nVidia Quadro K620 graphics card .
Is this an over kill , or on the right track?
Best regards
John
John,
What you have outlined is much better then what I use now and I wish I can have same hardware as you did. I whould do one more change if $ were no issue is to up Solid State Grive from 240GIG to 1TB.
How big and cmplex are yuor designs?
Regards, Yan
xPCB Layout(ExpeditionPCB)는 메뉴 또는 Automation script로 화면을 refresh하는 기능이 제공되지 않는다고 합니다.
우회할 수 있는 방법으로, 화면에 표시되는 영역을 조정해 보는 것이 떠오르는데, 아래와 같이 현재화면 (ActiveView)에 대해 Extrema, 즉 영역 범위를 인식시킨 후 다시 표시할 영역을 셋팅하는 것을 시도해 볼 만 합니다.
Dim oExtrema
Set oExtrema = oDocument.ActiveView.ViewContentsExtrema
oDocument.ActiveViewEx.SetExtentsToExtrema oExtrema
만약 위의 방법으로 되지 않는다면, 표시할 영역에 작은 변화를 주는 아래와 같은 구문도 생각할 수 있습니다.
Dim oExtrema
Set oExtrema = oDocument.ActiveView.ViewContentsExtrema
Call oDocument.ActiveViewEx.SetExtentsEx(oExtrema.MinX - 1, oExtrema.MinY - 1, oExtrema.MaxX + 1, oExtrema.MaxY + 1, False, epcbUnitCurrent)
또는, Automation script에 TransAction을 사용하여 데이터에 변화를 주는 부분을 감싼다면, TransAction을 commit할 때에 자동을 화면이 갱신되는 것을 이용할 수 있습ㄴ디ㅏ.
Transaction의 사용에 대해서는 PCB Automation Reference (expedition_pcb_auto.pdf) 의 Chapter 1 Examples of PCB Automation > Using Transactions 부분에 예제와 함께 자세히 설명되어 있습니다.
제 환경에서는 xPCB Layout에서 변화가 있는데 화면이 갱신되지 않는 것을 재현하지 못하여 테스트 해 보지는 못했습니다. 적용해 보시고 결과를 알려 주시면 많은 도움이 될 것 같습니다.
Created symbol for a part in xLibraryManager using a 0.5mm grid.
The part is then placed on xDxDesginer schematic which is also get to a 0.50000mm grid.
However when come to wire up the pins the wires do not attached exactly to the pins, there is a step between the pin and the wire. As can be seen in the red circles on attached picture.
How do we ensure that the pins on the schematic symbols are on grid when placed onto the schematics?
Should the symbol be created with a 0.1mm grid?
Is there a command that will auto snap the pins to grid either on the symbol or on the schematic?
(Using VX.1)
A couple of things to check - is the symbol editor set to High Precision (in the Symbol Property dialog) on save, this is needed for metric symbols on mm grids, it means you cannot use them in pre-iCDB versions of the product (2005 and earlier). If they are high precision then check the origin is also on a grid point, this might affect how the pins are placed.
If you move a pin in the symbol editor it will automatically snap to grid, you can't force off-grid items on grid if they're drawn that way, but you can snap symbols onto grid using the tool bar icon or from the Format menu.
Hi Yan
We do from really basic pcb 2 layer
To very complex 16 layer 4mil track and gap.
But it seems that after trails its more processor related
And lots of ram 16G or more .
We did a trail with the card that comes with the
VX.1.2 and monitored the pc's resources , cpu
Hdd, ram , graphics and watched how they performed
When moving and placing parts with bpoth 2D and 3D
Windows open .
And it seems as if the CPU is very impoertant with reasonable
Amount of ram .
So we will end up with :
Devils Canyon i7
16G fast ram
And a 970 nvidia graphics card .
Best regards
John
John,
I agree with you that most of CAD tools today are very CPU intensive applications. If I had a blank check, I whould buy fastet CPU, most RAM my hardware/software will support, biggest solid state drive and most imprtently a excellent graphics card with a good processor on it and a lot of RAM. You know as well as I do that CPU can unload most if not all of the graphics task to the graphics card procesor thus improving performance. In addition to that I will not buy today any laptop let alone a desktop where I wont be able to install 32 GIG RAM that CPU will use.
I hope this helps.
Regards, Yan
Hi, i am new to vesys, please help me out in solving this error, i faced issue while auto routing the wires in pro_e.
Steps followed for exporting and importing from vesys 2.0 to PRO-E
1. Created wiring diagram , exported it as .nwf file.
2. Imported in to PRO-E, as neutral file.
3. Created the network path between two connectors in PRO-E.
4. Gave reference desiginator and Entry port correctly.
When tried to do the auto routing, the error came as , "already the wires has been routed" also i have taken the screen shot of the error please find the attachment.
Thanks
Sharath.
Please take a look at Pro/ENGINEER, Creo Elements, Creo Parametric modeling prerequisites for use with Capital and for your situation, especially the last four bullets.
The Creo plugin does not support the network routing method where wires can be routed to individual cavities. In other words, the network segment must terminate on a csys that is designated as an entry port. Consequently, the upstream steps to set up a single csys for all wires terminating on a given connector are described in the four steps above and will help deal with error 3 in your report.
You can always delete existing wires from your harness .prt. They evidently have been created earlier, perhaps manually.
Hi Robert
Thanks for the reply, one thing however I need to know is where do I find the setting to High Precision in the symbol property dialog? Can you provide details of where to find this.
Thank you.
In the dialog where you add properties, it is above the properties but below the name - default says Backward compatible. Change it to High precision.
Sent from my HTC
Thanks for the help, setting to high precision has fixed the problem.
Now we got again the problem, time to bump this topic.
Mentor .dxf exports seems to be text elements for the texts.
Altium seems to generate lines as text (and no text elements)
The line version by altium would help our construction, but the dxf export function dosnt have any option for this.
There isnt a single option if im right? Im just able to select the layers i want to display on the dxf export.
Maybe this helps a bit to solve this problem.
George,
If I am understanding you correctly:
You listed a couple of requirements that you say you see no use for. Schematic symbol assignment to parts, pin assignment to symbols...... Things the packager pretty much handled for you before.
I'm working on making the migration from PADS Flow (Logic - Layout) to Central Libraries. So my perspective is that if all thing you see as useless are done well, I see no use for a packager.
And that might be the confusion created by the new Central libraries. They are trying hard to merge the best of both worlds, but those worlds were quite divergent.
Coming from my perspective, I think it's easier to understand the concept. PADS Flow libraries started with a Part Type. For example, a 74LS03 NAND gate. A Part Type is created, I'll call it 123456 (company part number). I add whatever properties I need (Part number, description, etc). I attach to that a NAND symbol. I can also attach another symbol, with a different graphic representation of a NAND gate. Then I assign pin numbers to the symbol. Then assign a PCB Decal, say a SOIC14. This lets me use that same NAND symbol with many different parts, with different pinouts (Quad, dual, single) and I can assign that SOIC14 to any other number of parts. As soon as you place the first gate on a schematic, all of the part information is there.
This is why you must have everything assigned in the Central Library.
Now, where it gets dicey is that xDxDesigner is symbol based, not part based. So the Central library is still driven by the symbol. So it's hard to resolve things like multiple symbols that describe one part, or duplicate symbols used to describe different parts.
The Mentor team took on quite a task to create Central Libraries that can be migrated to from both a symbol based, packager driven and a part based, library driven scheme. They are listening to users to get this right, but it's not going to be easy. I'm glad I read your post. I've been talking to Mentor about the frustrations I'm having migrating from PADS Flow, it's helpful to remember others are migrating from Netlist Flow.
Pete