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Re: Different width/gap on the same layer for Differential Pair

August 20, 2015, 2:54 pm
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Hi David,

 

Thanks for the reply.

 

I am mostly using Altium at my work, and doing such thing in Altium in design rules is as simple as breathing.

 

I'm struggling with PADS, about which I had a rather good opinion (thanks to hyperlynx and auto router) but as I have to do some simply tasks,

routes, almost anything this software sucks. I have been using mentor support, reading all comments, forums, etc and it always in PADS comes to such solutions.

 

My differential pair must basically have different width/gap coming out of the connector pins (pins located inside some other pins of the connector). Maybe it could be possible to place pads of the "component" inside there, however I don't know now. Perhaps I could remove those pins from the connector footprint and put them on the "component" so the connector footprint wouldn't change and also in the "component" put pads for wider differential pair outside a connector. But this solution horrifies me as I have multiple differential pairs...

 

Thank you once again for the reply. I am afraid that I don't understand the statement about unroutes in the correct order and reschedule command.

 

Best,

Pawel

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Re: Symbol Editor Preferences

August 20, 2015, 3:53 pm
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There don't seem to be many "preferences" that are sticky in the Symbol Editor. When you exit the tool the most of ini file is re-written to the standard defaults.

 

Idea D6595 discusses a different symbol editor issue but in the comments this preferences (pin spacing, colors, etc.) is called out and robert_davies indicates "not expected behavior" and "looking to address it in a future release"

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Re: Different width/gap on the same layer for Differential Pair

August 20, 2015, 4:49 pm
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The netlist in PADS is based on pin-pairs. A net with just two pins has one pin-pair. A net with three pins has two pin-pairs, and so on. (This is why you can't have single pin nets.)

 

You can assign a pair of nets as a differential pair that applies to all the pin-pairs of the net, or you can assign the individual pin-pair pairs separately.

 

The connections, or ratsnest, or unroutes, or whatever you want to call them, determine how the router works. Each of these represents an unrouted pin-pair.

 

The topology of the nets determines how the order of the connections is treated. (Setup > Design Rules)

 

Minimized is the default, and means you can route any pin of the net to any other pin or trace.

 

Serial, parallel and mid-driven are topogies for specific kinds of nets that need to be routed in a specific order. Almost all differential pairs are serial.

 

So when there's just two pins of a net, all the topologies are the same. When there's more, then you need to setup the pin-pairs to route in the correct order.

 

This is what the Reschedule command in Router is for. You can select the unroute, then the reschedule command, and are then presented with pins that are valid new destinations. Once they're in the correct order, you set the net to be protected, so no matter how the components are moved around, the routing order is maintained.

 

So my suggestion was based on the assumption your diff. pairs are just a single pin-pair for each net. My solution to route the net with two sets of rules was to break it up into two pin-pairs. A new part placed where the transition from one rule set to the other needs to be. You assign one pin-pair with one set of rules, and the other pin-pair with the other set.

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Information about the CCI-SCRIPT.txt file that is used to generate CCI database from SVDB?

August 20, 2015, 9:39 pm
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Hello,

 

I generate the SVDB database for a design using Calibre nmLVS, and next step I need to generate the CCI database based on the SVDB. Basically I used the script below to generate the CCI data:

 

calibre -cb -nowait -query ./svdb TopCellName < CCI-SCRIPT.txt > query.log

 

TopCellName is the top cell name of the design in the source/layout. Here I used the CCI-SCRIPT.txt file to control Calibre during generation. In this file there are three commands that I am not sure what they mean and what the number stand for. Could anyone provide me more information? Will really appreciate that!

 

#specifies GDS property values for attributes, corresponding to nets, instances and devices

  gds  netprop number 5

  gds  placeprop number 6

  gds  devprop number 7

 

Thanks!

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PADS Professional and Xpedition VX.1

August 21, 2015, 12:32 am
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Please help.

Is there any straightforward way of somehow converting or translating or import/export between PADS Professional and Xpedition VX.1 in terms of schematic, library and the pcb (vice versa)?

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Re: PADS Professional and Xpedition VX.1

August 21, 2015, 1:24 am
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To convert the library you must export the source in the EDX format then import this to the destination library using Import EDX, I believe this is documented in the on-line help for the library tools.

Once the library is converted you can import the design by firstly creating a new Xpediition project and then use File Import  PADS Professional. Set the library pointer in the project to the one you converted earlier.

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Re: Different width/gap on the same layer for Differential Pair

August 21, 2015, 4:09 am
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Hi David,

Thanks for clarifying, so I simply have to create a component with two pins and decal that is related to my wider width/gap.

 

Then in my schematic I have to put it and connect it to my differential pair, and then use pin-pair rules to change width/etc. in layout/router

Will it still route me my differetnial pair together ? I can't check at the moment.

 

Also another differential pair question.

diff.png

 

I would like to length match my other differentia pair (not the issue with different gap/width) in a matter as on the above image.

So when i routed out of the connector I would like to add small accordion to shorter trace to make them equal at that point (to match positive signal

with negative).

 

Is it possible with pads ?

 

Best,

Pawel

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Re: Error on generation of Cadence Allegro 15.Xx netlist generated from DX designer

August 21, 2015, 4:19 am
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I have changed the configuration file and illegal character errors are gone.

 

Still there are PINSWAP hertero device conflict error is there.

 

In my design now there are 5 error while generating allegro netlist. Could anyone know where will be the device files ? I could not find the device file in my working directory. I can export the .tel file but no device file is there.

 

Am I missing any setting in dxdesigner? Can anyone know about about howto generate the device files for allegro?

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Re: Error on generation of Cadence Allegro 15.Xx netlist generated from DX designer

August 21, 2015, 4:28 am
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It won't generate any outputs whilst you have errors in the schematic, you need to correct all errors before you can proceed. Looking at the errors the bad name error is due to the symbol name being 2INDDIO-B.n1 you can only have numbers after the decimal point as in 2INDDIO-B.1 etc.

It also looks like one error is caused because you have a space in the name of a component TIE BAR.

Not sure on the Hetero error, but it might be because you have pin swaps across devices.

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Re: Different width/gap on the same layer for Differential Pair

August 21, 2015, 4:59 am
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That's a terrible pinout for differential pairs with that connector. I feel your pain.

 

Yes, you can add the accordion, but only manually after the pair has been routed. The smaller grid you use, the easier it will be. I should mention I route all of my differential pairs manually, and can offer no help if you want to do it with the autorouter. I do all my length matching manually using the spreadsheet view for length checking, and for complex topologies, an actual spreadsheet.

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Re: Different width/gap on the same layer for Differential Pair

August 21, 2015, 5:05 am
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Hi David,

 

Yes the pain is really big I can't really say what it was done this way....

 

I have also routed them manually. I will try to use the spreadsheet view in pads router.

Is it easy to use ? Perhaps i will find some info in support.

 

Thanks.

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Re: Plane area cutout stuck

August 21, 2015, 5:21 am
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Here it is 3 years later and I came across this same issue. For me the SPO worked, so far. I have had the void "return", but so far so go.

 

Thanks,@DenisL

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Re: Symbol Editor Preferences

August 21, 2015, 5:31 am
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Hi Shannon,

 

Is it possible to copy the .ini file to a company standard location than edit it, maybe in the future? I would like to automatically add certain attributes to the custom symbols the engineers are designing. This would speed up releasing my library symbols in the future. The more I can do to pre configure the symbol creation process the less chance of errors before it gets released.

 

Thanks

 

Kirby

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Re: netlister updating PKG_TYPE

August 21, 2015, 6:17 am
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Thank you for this info, greatly appreciated! I hope you have a great weekend!

 

 

Greg Deakins

CAD Librarian/Administrator

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Re: Symbol Editor Preferences

August 21, 2015, 6:46 am
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Not until we ship a new editor with the VX.2 release. This will be based on xDX Designer and so will sue the configuration files and processes supported by xDX Designer regarding corporate settings.

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Re: I want to modify the Part List Exclude in the Property Definition Editor in PADS 9.5

August 21, 2015, 7:04 am
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Hi Robert,

 

is this something that may get modified in the VX.2 release? My impression is this isn't really an issue for most people.

Thanks

Kirby

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Removing an old board outline

August 21, 2015, 8:33 am
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I am currently working on a board design that started out one size of Board Outline, then got changed to a second a different size. On the design screen I see the second - and, correct - board outline. However, when I go into 'Create PDF' I see both the old and new Board Outlines. Just in case this was an image artifact I went into CAM and created some artwork. The 'old' board outline also appears there.

 

Can someone point me in the direction I need to go to remove all remnants of the 'old' Board Outline ?

 

Thanks,

 

Mr. Amalfi

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Routing nets connected to a plane/copper pour

August 21, 2015, 8:42 am
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When using a plane/copper-pour layer is it necessary to physically route the connections attached to that plane ?  I.e., I am using a copper pour layer connected to the net 'GND'. I have many components which are connected to the 'GND' net. I routed some of these GND connections, however, when I go into 'Verify Design', I am getting many (para-phrased) 'Error, Subnet of net 'GND' I feel this may be due to the fact of these individually routed 'GND' net connections.

 

Is this similar to the case when stitching vias, i.e., they don't actually get routed, they are just connected between the plane layers ?

 

Can someone please clarify ?

 

Thanks.

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Re: Expedition - How do I select and move a bunch of components over on the PCB to make room for a component I forgot to place

August 21, 2015, 10:31 am
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(update to the "Circuit Move and Copy" comment above, related to "off-grid" copies).

 

I just realized that I was skipping one crucial step which was causing all my moves and copies to be off-grid

When using the "Edit/Circuit Move and Copy" command, after everything is selected that you want to Move or Copy,

when you start the Move or Copy, the items will be attached to your cursor at a calculated midpoint of the selection group
(which is almost always "off-grid" !!!)

SO,

when you set the moved or copied group down, the components and vias won't match any grids you have set in your Editor Control dialog box under the "Grids" tab. I had gotten into the habit of using the Place/Snap-to-Grid command after "Circuit Move and Copy" commands, but it sometimes alters the routingHOWEVER,

if you "right-click" after the selection is made, BEFORE you start the move or copy, you can SET ORIGIN to a via or component pin (or anything that is currently "on-grid"), and THEN execute the Move/Copy command. Then you won't get any errors or warnings about "off-grid" items in the DRC check

 

I had seen the right-click menu before, but got confused by the SNAP options. SET ORIGIN works!

 

hope that helps,

Jack

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USB Dongle Occasionally not detected

August 21, 2015, 3:48 pm
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I use a USB hardware dongle. Occasionally, during program use, I get an error saying that my key isn't detected. Sometimes when this happens I just clear the error and keep going. But sometimes the program exits abruptly. So a couple of times I've lost changes.

This has been happening for a long time, maybe ever since I've been using the software (over 4 years). It may be happening more often, not sure, but I would sure like to know if this is a known issue and if there is a solution for it. Thanks in advance.

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