Thanks for your reply.
I am getting this error while import
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Re: How to create Mentor keyin netlist from Orcad 16.6
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Re: How to create Mentor keyin netlist from Orcad 16.6
Hi,
I don't have and so I don't know Orcad/Expedition Interface option.
It's about 15 years that I use Expedition using Orcad netlist without using this cost option.
All works fine.
I think you must read installed documentation. Usually Mentor help documentation is good.
Regards,
Bortolo
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Re: Does VX1.1 have the ability to create SRP sheets or similar?
Is this looking for automation to do this or should this post be general under Xpedition?
You should post an enhancement request on Ideas or promote D3209 on the DxDesigner ideas pages
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Re: Filtering a component collection
Hi joseph-san,
It's an example.
cellList = Array("Cell-A", "Cell-B", "Cell-C")
Set cmpsColl = pcbDocObj.Components(epcbSelectPlaced, epcbCompAll, epcbCelltypeAll, "*")
For Each cmp In cmpsColl
For i = 0 To UBound(cellList)
If cmp.CellName = cellList(i) Then
'---- RefDes move process ----
End If
Next
Next
Satoru
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Re: PCA_CPU partition with DC to xDX translation?
The symbols in question most likely are orphaned in the DC schematic, that is they don't have equivalent symbols/parts in the Central Library any more. In which case the translator can't determine where they come from and assigns them some reference based on the hierarchical path in the DC schematic.
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Re: Does VX1.1 have the ability to create SRP sheets or similar?
In the old toolset we used SRP, which was/is a standard, off the shelf MGC item.
What’s the equivalent in the new toolset? Our guys want the extra sheets generated by SRP as it is very useful for the manufacturing process.
So my first enquiry was to simply establish if there is the ability in the new toolset to emulate SRP.
If not, then an enhancement request will be made.
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Re: Does VX1.1 have the ability to create SRP sheets or similar?
So the post belongs under Xpedition or xDX Designer rather than Automation, so we will move it.
The short answer is no there is no equivalent of SRP, hence the suggestion to vote for D3209 on Ideas.
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Re: Create Variant Manager report from a VBscript
Hello Nathan
I am very sure that it can be done. Attached please find a script that will help you in your quest, I hope. It is started from inside DxDesigner (Open File - set file type to .efm)
This script produces a txt file - then gives the option to reformat the output. I just provide this as an example. It is not written by me, I just happened to pick it up at one point.
Anyway - the reformatting is probably not relevant - so skip that.
Have a look at the Sub ButtonCreateVariantBOM_EventClick()
To start, you will have to figure out the important parts that start with vmbom (these are all the setups)
Importnat, since you want to create Excel files, is the vmbom.Format - it is set to 1 (for txt) but needs to be modified to 4 (xls)
vmBOM.Format = 1
changes to
vmBOM.Format = 4
I believe that just doing that (and getting rid of the other (Reformat ) button will get you started.
Somewhere I have another script, that starts outside of DxDesigner - if you are interested, let me know, and I'll find it. If I remember correctly, it starts DxDEsigern in the background, and chucks out Variant Boms for all variants.
For the details, make sure to take a look at the documentation : eevm_auto.pdf in your local Mentor folder...
I hope this helps...
/Peter
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Connectors not exported to Vesys from CREO
HI All
Anyone encountered a problem when exporting an xml file from CREO to VEsys via the bridge. The harness appears with the correct length, but connectors are ommitted.
Thanks
Vinnesh
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Re: Wire colour doesen't appear correctly in Vesys Harness
Hi!
I solved the color problem a few weeks ago, just I didn't have the time, to write it down jet.
So the main problem was about my predefined color names. I recognized in the wiring diagram, that the wires have a primary color of "M", but this color doesn't exist in my color codes, but my predefined color codes were all "M-Bl", "M-Rd" etc. so it seemed, VeSys doesn't support dash mark in color codes, and of course that was the problem. So if you are defining colors your own, don't use a dash mark, I hope this will be helpful for someone.
Regards
Lac
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How to import Eagle files to DxDesigner?
Hello all,
I am trying to convert some Eagle files( .brd and .sch ) to DxDesigner? I want to modify these files in DxDesigner/Expedition 7.9.3
I have asked a similar question before on this forum but now I have PADS Standard Plus installed. I found on other forums that I can go from Eagle to Altium to DxDesigner but I can also use PADS.
I currently have installed Mentor Graphics Dx/Exp EE7.9.3 and I need to use this version for the Eagle files to make changes.
Is there a way to do this?
Thank you in advance.
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Re: AATK menu not showing up in ExpPCB or DxD after ENV AATK and WDIR are set correctly
Hi Kendall: Thank you for your quick response and recommendation to use RapidEE! I finally got a chance to get back on the user's machine, when opened RapidEE, I immediately noticed the user has a user variable of WDIR that overwrites the system variable WDIR, and caused the AATK menu not shown up.
Thanks again!
Ping
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Re: Generating layer stackup in drill drawing in PADS Layout
Hi
Tried the script and it works fine but it lacks the feature of single sided board.
The reason I mention this is that I’ve don a script were this feature is missing as well.
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Re: Generating layer stackup in drill drawing in PADS Layout
Hi,
Can i use the same script for expedition 7.9.4 version?
Regards,
Sajiv.
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Re: Plane shape couldn't connect vias/pin
Hi,
I think in your plane classes you have to assigned spokes for vias. Make it as a buried one. Then only all the vias gets connected together.
Check your plane classes.
Regards,
Sajiv.
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LVS step Netlist vs Netlist
Hi all.
I am using Calibre LVS to compare two netlists.
I got a netlist by using S-edit, the second is derived from the GDS file.
But when I run the comparison, I get the error:
Source netlist references but does not define 2 subckts:
nmos
ptos
If I define nmos and pmos, I see in the report that the LVS see different instances.
This is a mistake netlist from S-edit or LVS is not working properly? How to fix it?
my netlist from S-edit: http://paste.fedoraproject.org/236140/14351523/
me netlist from LVS: http://paste.fedoraproject.org/236144/14351526
lvs report, when defined nmos & pmos: http://paste.fedoraproject.org/236145/15272314
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PADS Translator Tool
Hello,
Does anyone know if the PADS professional VX 1.1 come with a PADS Translator from Altium to Expedition?
I recently downloaded a 14-day license from PADS Professional Evaluation Download - Mentor Graphics .
I tried looking for the Altium translator under the Translators folder but I only see:
Allegro to PADS-Pro VX.1.1
DA to xDx Translator VX.1.1
DC to xDx Translator VX.1.1
DLib to xDx TranslatorVX.1.1
I am not sure if it was an installment issue~
Any help is appreciated.
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Re: PADS Translator Tool
Marissa
The Altium to xDX Designer translator is included in xDX Designer under File > Import...
For Altium to Pads Professional PCB Layout Translations, it is also included and is a standalone command Alt2PE.exe located in the software install directory.
All of these Migrations are explained in complete detail on Support Net on the Migrations page.
Thanks
Vern
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Altium to Expedition PCB 7.9.3 translator?
Hello,
I am trying to import the layout of a file from Altium to Expedition PCB.
I am able to import the schematic from Altium to DxDesigner but I am trying to figure out if I can directly translate from Altium to Exp. PCB.
I am currently on the version Mentor Graphics Dx/Exp EE7.9.3.
I found a pdf (attached) that shows how to go from Altium to Dx/Expedition but you have to go through PADS. I currently have installed PADS Professional VX1.1.
I am not sure if the new PADS version will translate to the 7.9.3 Expedition since it is newer than Expedition.
Can I go around PADS or do I absolutely need it to get from Altium to Dx/Expedtion?
Any help is appreciated.
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Re: LVS step Netlist vs Netlist
My team uses an in-house portable design kit for everything, so your problem sounds very familiar.
We have schematic symbols that dump MOSFET cards with the model names "N" and "P". For LVS, we then map the model names with scripts to whatever the foundry's Calibre deck requires.
Now, in my experience, foundries tend to have LVS and PEX extract MOSFETs to subcircuit cards (whose lines start with "X"), but they are expecting the schematic to provide MOSFET cards (whose lines start with "M"), so there's some mapping going on in the Calibre deck between schematic MOSFET cards and extracted subcircuits. What we tend to see a lot is a very similar error which shows up when we forget to map the MOSFET model names to whatever the Calibre LVS or PEX deck is expecting. Looking at your netlists, you seem to have something else going on. It looks like your S-Edit netlister is netlisting your MOSFETs to subcircuit cards that start with "X", while the netlist Calibre extracted from your layout has MOSFET cards that start with "M". I expect all you have to do is change your S-Edit source schematic's MOSFET cards so they start with "M" instead of "X".
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