The holes are a miss. Read this thread. 3D Export of holes
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Re: 3D PCB
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Re: PADS Layout need username and pssword?
Could be someone on the IT side changed permissions with or updated FlexLM. I never seen anything like it though.
c
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Re: 3D PCB
Yup remember this, but that was really more for IDF out, would have thought Mentor would have improved this by now!
With all the new 3D capability.
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Re: PADS Integrated Flow with DxDataBook
Create or save a .prj file with the path to your central library path .lmc file. Put the ,prj file in your templates folder.
No way to edit more than one part at a time that I know of.
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Re: 3D PCB
I had these same questions, and spent a week or so back and forth with technical support to get the answers, and am still waiting for some, so here's what I know now.
- The Library for 3D mappings in the netlist mode is in your Reuse directory, and that's setup from your Options/Global/File Locations of Layout.
- The Library is not a single file, but a group of sub-folders and files.
- Your local mappings are in the directory that contains the PCB, in a folder that gets created with the same name as the PCB.
- Local Mappings are written to the Library with the Update Library command in 3D View.
- To update other designs with existing mappings, use the Update Models command in 3D View. The mapping must be in the Library, and part name and decal of a component must match.
- There exists as of the date of this post a bug with Library mappings that affects the exported step file.
- Board cutouts of any shape will create an opening in the board outline step file, so adding circular cutouts where your mounting holes are are a workaround.
- Parts with a single hole, like mounting holes, that are non-eco registered will create holes in the board outline step file.
- I was told that adding a "HOLE" attribute to a part (or maybe the decal?) will create a hole in the board step file, but I don't know how that works yet.
- I was also told of a "FIDUCIAL" attribute, but I don't know how that works either, and has nothing to do with your questions.
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I have to retire my current license server.
How do I get my licenses file updated to use the new host ID?
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Re: Wires remain after Synchronize from old design
Monte,
When you are trying to do synchronization connector and splice are replaced from schematic, But the wires will be added and the existing wires will not be deleted because there may be a chance for , This will cause packing of two wires in single cavity in a connector because of existing wires may have different attributes with schematic wires.
To avoid this While doing the synchronization you have to delete the existing wire in the harness before starting synch process.
Find the below image for your reference.
Doing synch without deleting existing wires,
Doing synch after deleting the existing wires,
Regards,
Manoj K
+91 8973234943
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Re: xRC: How to extract parasitics w.r.t local substrate?
Hi Vern, thanks so much for your reply. It seems that indeed it's complicated and I will take some time to get this figured out, so I'll leave it for after-tapeout mode. I'll come back here to comment on what I find (unfortunately I am a PhD student so I have no posting rights in SupportNet )
I am wondering though how this issue is handled in real world designs. I find it hard to believe that verification people just make amends with the idea of having all the parasitics tied to the same node when simulating chips with multiple power domains!!!
Cheers,
Jorge.
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Re: Copper Pour not flooding solid
Would you mind explaining what you mean by "It was the line width in the Drafting Properties for the pour outline"?
What makes me nervous about your answer is that sometimes I change the line width for pours so it can do a better job of pouring between features (and not leave "slots" in the plane), but I wouldn't want my pours to be hatched.
Why wouldn't a smaller line width cause the pour to draw the lines closer together, instead of leaving gaps?
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Re: White space in netnames of XDX schematic
Reading this makes me wonder if there is any PROBLEM with using spaces in net names?
I suppose if the VERIFY checks don't look for it, it must be okay, which is why I'm asking.
Jack (aka "the new guy")
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how to generate back annotation file (from PADS layout) to import in orcad schematic ??
Hi everyone,
i have the PADS layout file and Schematic in orcad(.dsn) file.i did auto renumbering (Ref des changes) ,that list should be implement in orcad schematic (back annotation).i could not synchronize pads layout in orcad file. is there any option to do the back annotation from pads layout to orcad schematic ??
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Re: How to merge diffirent PCB design
I'm a Boardstation/RE user and have never used PADS and don't know the official answer,
but since no one else has taken a crack at this question here are some considerations:
- Since the layout is driven by the schematic, it seems like you would have to combine the schematics first
- I'm not sure if PADS supports blocks or re-useable circuits, but maybe you can plop the individual pieces into a design using that kind of functionality
- If you just need them combined for manufacturing, you may want to find out if you can combine layouts on a fabrication PANEL or assembly PALETTE design, if your software supports that
Again, I'm not familiar with PADS, just trying to help,
good luck,
Jack
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Re: Cross-Probe Between DxDesigner and Autoactive PCB Browser
Why do you say visECAD is not a useful tool for review?
I have only looked at it for an hour or so, but it looks powerful.
(or, were you saying visECAD itself is too expensive?)
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Re: Copper Pour not flooding solid
Hi Jack,
The setting I am referring to is shown below. When I have it set to 1 my flood area will have the mesh patter shown to the right of it, and will show in the Gerber file the same way.
Now when I change the line width to 25 the flood is solid, and looks correct in the Gerber.
I talked to a support guy about this a few years ago and was told that it was in relation to line width being small to something else but I don’t remember what that was. It wouldn’t be a big deal if it didn’t mess with Gerber data but since it dose I keep an eye out for it. This is really all i know about it. I don't know why this happens.
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Re: Meaning of "Allow one additional via per SMD pin" at the Editor Control
I think this setting might only be useful if you have "Prevent Loops" set as a route control,
(I've had trouble placing extra vias with the "prevent loops" setting turned ON),
Also, in your DRC check, the extra via won't be flagged as a "hanger"
I suspect this is an old setting that is not very useful anymore,
now that we can do things like multiple thermal via grids buried into power pads, for example
Jack
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Re: how to generate back annotation file (from PADS layout) to import in orcad schematic ??
You need to use the .ECO log file that PADS created when you did the re-number. You will need to edit the file, removing the header/footers and rename to .SWP file. Then you can point the the SWP file in OrCADs Back Annotate window.
c
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Re: 3D PCB
Guess what I have just been thru same path late yesterday and was about to post results, but your response pretty much sums it up.
We had some discussion over holes and it does not seem to me Mentor will be adding functionality to include all holes in design in any 3D output.
Vias I can understand. Possibly can understand all thru holes within parts, as you do seem them when lining up solid models and the Pads do come thru
in 3D output, so I guess that is OK. I still think the whole hole thing is a bit hokey still I mean the only way hole will automatically export 3D are non-eco
however if you need a plated mounting hole it really needs to be eco if you want connectivity to update. So the whole idea of adding these extra attributes is well hokey, I still say just export all holes period and be done with it. But I know Mentor is still working to improve the 3D functions & it is the first release
of this level of capability. I know they are working on it, but the whole library situation needs work in both flows period, not quite there yet. Also the update or change to a mapped model in netlist flow is a bit more cumbersome than Integrated flow like you say bunch of files in bunch of folders.
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Re: Copper Pour not flooding solid
Unless I am misunderstanding, that behavior is VERY different than what I've seen (I'm still on AutoActiveRE, unfortunately)
If you use a 25mil line width to draw your planes, the copper will not be able to fit through the spaces between through-hole vias
(unless you use an absurd via-to-via spacing rule) .
The planes on our designs would look more like swiss cheese than good copper fill.
There HAS to be a way to set a smaller aperture and still have a solid plane
sorry I could not help you,
Jack (aka "the new guy")
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Re: SYMBOL SIZES
Hi Nuri, Thanks a lot about the tips!
I was having some problem....symbols were coming too big! I was changing the "Grid Spacing" and didn't change anything.
So I saw your comment about only get grid spacing information when the diagrams are created, so I deleted current diagram and created news.
In news diagrams the grid spacing already is coming ok and the symbols already are in good size.
Thanks by the tips!
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Re: How to import a Cam Document by using a Macro
Here's some code (script NOT macro) that seems to work:
Sub Main
CAMdir$ = Application.GetConfigParamString("directories", " CAMDir", " C:\PADS Projects\CAM\default")
CAMfile$ = GetFilePath(,"CAM", CAMdir, "Pick a .CAM File to Import",)
If CAMfile = "" Then End
ASCfile$ = Mid(CAMfile,1,Len(CAMfile)-3) & "ASC"
ASCheader$ = "!PADS-POWERPCB-V9.0-BASIC! DESIGN DATABASE ASCII FILE 1.0"
MISCheader$ = "*MISC* MISCELLANEOUS PARAMETERS"
Open ASCfile For Output As #1
Print #1, ASCheader; vbCrLf
Print #1, MISCheader; vbCrLf
Open CAMfile For Input As #2
While Not EOF (2)
Line Input #2, L$
Print #1, L
Wend
Close #2
Print #1, "*END*"
Close #1
ActiveDocument.ImportNetList(ASCfile)
Kill ASCfile
End Sub
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