Hi Nate,
I've had a very similar issue recently. It turns out that the IBIS model provides two slew rates, the slow one being the default. In my case I need to pick the fast slew rate. Once I made the correct selection the eye diagram looks right. Hope this helps.
What is a more common way to name a header or socket? I've been calling headers hdr2x13 but what about a socket?
Thanks
There's a lot of information on this message if you search for it. For example:
Cannot start the service "Interactive Services Detection" in - Microsoft Community
Hi all,
How can I make the layout project for a concurrent design enabled xPedition project ? When I tried to make the layout file at the server location it give me an error.
What is the solution for this?
Thank you
It seems you have a hybrid setup based on the ODA parts. If you are using the Integrated flow with a Central Library then the Supply Rename is used to override power/ground pins defined implicitly in the mapping and the Signal property shouldn't be on the pins at all. These are used for a netlist project using the PCB Interface to annotate back and forth.
If using Hetero type 2 then the picture I showed you is for the netlist flow, the same set-up can be created in the Central Library without the need for many of the properties.
It is good to know however that either method works in your case (renaming the Signal property and Supply Rename), but personally I would figure out which mechanism I'd prefer and create my components accordingly.
The dialog shown is for the VX.1 version of software, it was re-arranged and a couple of bugs/enhancements made, but generally they work the same.
Community_Admin Is there any chance that the Community interface can be changed to provide a link to 'News' from the main menu bar?
It seems that this is now the preferred mechanism for the Jive Community software and it would be very useful.
Thanks,
Simon
I am using QuestaSim for Verilog simulation. The simulation need some systemC functions for co-simulation.
Here's where I encounters the problem:
First I compile the .C file into .o file
~/mentor/release2015/questa_v10.4/questasim/gcc-4.7.4-linux_x86_64/bin/gcc \
-lz -std=c99 -c -g -fPIC -DMODELSIM_VPI -fno-stack-protector\
-I/imec/software/mentor/release2015/questa_v10.4/questasim/include/ \
../src/elf-loader/elf-loader.c ../src/elf-loader/vpi_wraper.c \
../src/jtag_vpi/jtag_vpi.c \
I get no warning or errors. Then I generate .vpi files from the .o file, again no warning or errors:
~/mentor/release2015/questa_v10.4/questasim/gcc-4.7.4-linux_x86_64/bin/gcc \
-lm -lz -shared -Bsymbolic \
-o jtag_vpi.vpi jtag_vpi.o
~/mentor/release2015/questa_v10.4/questasim/gcc-4.7.4-linux_x86_64/bin/gcc \
-lm -lz -shared -Bsymbolic \
-o elf-loader.vpi elf-loader.o vpi_wrapper.o
Note That I have two vpi: jtag_vpi and elf-loader. Then I start QuestaSim loading those two vpi.
vsim -c -L work -t 10ps work.dut \
-pli jtag_vpi.vpi -pli elf-loader.vpi
jtag_vpi is OK. However, The other elf-loader keeps generating errors that I never get it right by trying out all the gcc configurations I know.
# Loading ./elf-loader.vpi
# ** Error (suppressible): (vsim-3197) Load of "./elf-loader.vpi" failed: ./elf-loader.vpi: undefined symbol: elf_strptr.
# ** Error (suppressible): (vsim-PLI-3002) Failed to load PLI object file "./elf-loader.vpi".
I have been working on this for few days and really appreciate if anyone will help.
Seems to me that ModelSim missed some libraries (e.g. for elf_strptr) the elf-loader.vpi is using. But in GCC there's no warning of that, meaning GCC can find those libararies, but not QuestaSim, why?
for the record: here's uname -a:
Linux MY_SERVER 2.6.32-431.el6.x86_64 #1 SMP Fri Nov 22 03:15:09 UTC 2013 x86_64 x86_64 x86_64 GNU/Linux
Hello
I have problems simulating simple schematic contains few capacitors, LEDs, resistors, two diodes,... and buck LED driver (AL8807). I downloaded SPICE models for most of the parts and also for the driver, transfered them by Tools - Convert Pspice Libraries. Than load transfered files into schematic as SPICE models. After run the simulation it crashes on the error mentioned above.
Simulation of the same schematic in LTspice works well. So I expect the spice model should be correct.
Do you have any experience with errors in diablo functions in spice models?
I attached downloaded (not yet transfered) spice model in my post. Can you check it out, if my way of transfer is correct.
Thanks for any advices about this topic.
Looking a making the jump from DxDesigner Netlist flow to the PADS Integrated flow for our design team?
Has anyone made a successful transition? Was it very difficult for you? Any problems that you ran into?
What are the pros and cons of moving to the Integrated flow?
I have been playing with the netlist to integrated library conversions and it has been a headache. Most of the hetro part must be redone and don't migrate over without extra work.
I have some duel symbols that share a common pin between the two instances and this will no longer work. I am told that each instance must have a different symbol in a central library.
Please share any of your experience with this whole process.
John W.
Hello All,
We are using PADS Layout 9.5 to design a custom interface PCB to interface with a UUT using a test fixture with double-sided nails. This means that the bed of nails will touch test points located on the bottom of the UUT on the top of the nail while also touching a test point located on the top of the interface board with the bottom of the nail. In other words, the UUT and Interface PCB make a sandwich with the nails in the middle.
Our biggest challenge with this is that we need to layout the custom interface PCB so that the test points on the PCB matches exact coordinate locations of the test points on the UUT. We would prefer to have an automated way of doing this to not only save time, but also greatly reduce chance for human error (since we have 150 or so test points). The fixture house gave us a 1:1 DXF file that we can bring into PADS which has all of the test points present as simple 2D circles. The manual ways to do this would be to create test point components in the design and manually overlay the test point component onto the DXF test point circle, or manually type in coordinates for each test point. Any ideas for how to automate this, either with ASCII file or DXF manipulation or something else, would be greatly appreciated.
Thanks,
Gabe
While trying to install a renewal license, all but a couple of the Start Menu links disappeared under Mentor Graphics SDD. Do I need to run through the product installation again to get them back or is there an easier way?
Thanks
Hi Gabe,
I can't say I know how to do this off the top of my head, but I think Automation can handle this. You probably want to check the PADS Layout Command Reference Manual but I can see some code snippets suggesting this would be possible. The Pin.TestPoint page gives the following code snippet, which removes all test points from the design and then adds one top layer test point per net on an arbitrary pin:
Sub Main
' Remove all test points
For Each nextPin In ActiveDocument.Pins
nextPin.TestPoint = ppcbTestPointNone
Next nextPin
' Add one top layer test point per net
For Each nextNet In ActiveDocument.Nets
Set arbitPin = nextNet.Pins.Item(0)
arbitPin.TestPoint = ppcbTestPointTopLayer
Next nextNet
End Sub
There is also Report Generation Language (RGL) syntax described which can report the (X,Y) location of pin & via test points, whether a net has a test point assigned, the total number of test points, etc. See the file Test Points.BAS mentioned in the document. This may be handy to check the test point locations against your ASCII list if you do end up adding them manually.
Perhaps you can add vias by (X,Y) coordinate and then set the via type to test point with the PPcbTestPointType command?
Hi,
In the PADS Standard Plus, is Logic for design entry available? Is a license for Logic included?
I know in VX1, you need to download it separately.
Danny
If in Logic and build a part, in the pins tab I have a pin type of Ground. When adding connections in Logic, I noticed I can connect a Ground net to the Power pin. Is there a DRC check to make sure this can't happen?
It just stung one of my engineers, as he did not rotate the part and tied a GND net to the PWR pin, and PWR to GND pin. Rework now.
Why can we specify the Gate and Pin Type as something, only to be allowed to connect anything we want to it? Am I missing something? Is there a way to check for this?
Thanks,
Gary
Hello,
I don't know if you have enough information to provide a good response. Looks like you want to use Xtreme on this project however the message you show is from the Job Wizard. This message almost seems you are using xDM Design for data management?
If your issue is specific to concurrent design having multiple users operate on one PCB Design, have you first setup the iCDB RSCM server so the design can be used for concurrency with multiple users? Have you tried starting the XDS on this design and attach to is with a Xpedition Layout Client?
A lot of guessing is going on so if you can provide more details maybe someone will be able to help with a solution.
Thanks,
Jerry Suiter
Product Marketing Director Xpedition
Hello,
Have you verified that the layer/Net combination in Plane Assignments is set to be dynamic allowing the metal to be generated? Looks like to me the state is draft/static for the layer/net thus no plane metal/connections are created.
Other things to check: Verify you plane Hatch/clearance for the Plane Class is not set to some bad value.
Regards,
Jerry Suiter
Production Marketing Director Xpedition
Hello,
You can use the Mask Generator to do this check. Extract one of the nets, expand by the max clearance and use the subtract operation with the other trace. The result should be areas where the trace is < your max clearance.
Regards,
Jerry Suiter
Product Marketing Director Xpedition
Hello,
I agree with Vern, it would be best to contact CSD with such a question. Based on what I see, to me it appears the line at 45 degrees is already not on the grid defined. If you have an object off grid and move it, it does not snap to the grid but keeps it's relative distance from the grid. So if I place a line on a 10th grid, then change the grid to 20th, the line will move in 20th increments but remain on the 10th grid it was placed on.
if this is your issue, this is not a bug but by design and it's up to the user to first snap the object to the grid if they wish it to be on a new grid.
Regards,
Jerry Suiter
Product Marketing Director Xpedition
Hello,
This is a good question. If your not using xDM Library (old DMS) you can not import/map and align 3D models at the library level. The 3D Library Flow requires the xDM Library (DMS) system to manage 3D models and distribute them to the design community.
However we are enhancing our 3D Designer flow to allow 3D model imported/mapped and aligned within Xpedition Layout to be reused in other designs by pushing this information back into a centralized location that can be shared with other designs. We do not concider this 3D Library Model management but more like Reuse and sharing between users/designs. This should be released early next year.
Regards,
Jerry Suiter
Product Marketing Director Xpedition
