Hi
Anyone know how to select a parttype name in Excel - and then add the part to a PADS Logic schematic?
I am considering this process:
1) Selecting a parttype name in an Excel spreadsheet.
2) Click on a button (macro) in Excel will add the selected part to PADS Logic.
Just as when clicking 'Add part' directly in Logic.
Take a look at the attached image.
Regards
Klaus
Hi Klaus,
There is a piece of software called ALE (Advanced Library Editor) - You should be able to extract parts and their associated attributes. See:
https://communities.mentor.com/docs/DOC-2383?z=9AoHd5
Dave
Hello:
Can some kind soul please send/or describe the contents of this technote for me. I cannot access it.
Thanks In advance,
Terry
Hi Terry,
We can't post TechNotes here on the Mentor Communities because they are protected content on SupportNet for people with support contracts. The Communities are open to everyone regardless of support status but we can't access the same info on SupportNet.
I don't have much experience with xRC but this seems to relate to bad devices, possibly identified during the connectivity extraction phase of LVS. If you're getting bad device warnings they may need to be dealt with before xRC can proceed smoothly.
Anybody else out there with first hand experience of a problem like this that could offer some tips?
-chris
Hi Phil,
Is this still an active issue for you? You raise several good points and I might be able to help with many of them. One thing that caught my eye was this:
> Presumably LVS is not flagging this as a comparison mistake because it already
> announced it would not compare some of the pins via the NON-IDENTICAL PINS message?
LVS should fail due to this, so you shouldn't be able to get a clean LVS, it just so happens that it's not reported as a "discrepancy" the way you might expect other kinds of connectivity errors to be reported. It should be reported like this:
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Components with non-identical signal pins.
A "warning" would usually allow LVS to be correct if everything else is ok but this non identical signal pin should be an error that forces LVS incorrect.
"Signal" is an important distinction here. LVS can issue a very similar message for "power or ground" pins and due to the way power and ground often propagate through the design with name changes along the way, differences of that kind can give a "warning" instead of an "error". The lvs power and ground name statements can be used to indicate which nets should be considered as power or ground rather than signal pins and you might control the behavior in that way if it works well in your flow.
Hi David
I guess the ALE software is for DX-Designer only?
I should have wrote that I am using PADS Logic / PADS Layout.
regards
Klaus
Is there a way to assign design rules to an unconnected standalone pin? For example, there is a relay with an unconnected pin that may or may not be switched to AC Hot/Live during the circuit operation. As such, I would like to enforce the relevant creepage and clearance distances to that pin. At the moment, I can only see a way of assigning rules to Nets however a single pin net automatically gets deleted and the rules are not enforced. I have an inelegant solution of keepouts on the pins but would like to use the proper rule system.
Hi everyone,
i am new to Dxdesigner.Right now i am learning Dxdesigner.i added Border.i need to edit the property how to edit the property.is i possible to create custom border.Let me explain any one.
i need to edit the red section in border.
Klaus,
It looks like this is the case :-(
It may be worth double checking with the contacts shown in the top of the link (Created by scott_williams on Jan 6, 2011 8:01 PM. Last modified by jeremy_parker on Mar 12, 2015 3:58 PM.)
Dave
These two properties are autogenerated and updated from Tools - Update Other Objects: Select Properties and Print Order. If the sheet border is correctly set up the Title is the schematic name, to change it edit it in the Navigator view and propagate it to the sheets using the above command. The sheet 1 of 1 should be the following two properties @PRINTORDER and @SHEETTOTAL.
You can check this by using the Border Properties command from the context menu on the right mouse button if you click this whilst in an empty part of the sheet (no objects selected). You can edit the border properties in the Property Dialog using this command, but it only affects the current sheet, and you should really propagate these values throughout the design to ensure the correct sheet numbers and sheet total.
Also look at this discussion Re: Defining border attributes and border.ini file location
Thanks for your reply.
but i need to update the title block and Revision i could not update it.i am following Dxdesigner with pads flow.so how to do it
Can you reply for following question also,
1.where i need to assign decal name in symbol.
2.how to generate the net list for Pads flow.
To update the other items you edit them from the settings dialog (read the other post I referred you to, you can ignore the comments about DC). The 'user data' such as Revision, Author etc need to be in your property file in order to have this work correctly (I suggest you read the manuals on this).
From the other post "The data (apart from the @ properties) are edited via the Setup - Settings dialog. Look in Setup - Settings and under the Boards section you will see the Borders sub-section."
Title block needs to be changed in the Navigator: See the snip attached. Click on the Highlighted text, RMB - Rename. Type the name you want then run Tools - Update Other Objects - Properties to propagate the change to the sheet.
Decals are defined using the PKG_TYPE property. The netlist is generated from Tools - PCB Interface.
If you are still stuck go to SupportNet and search for more information.
the latest pads release VX1.1 supports only 64 Bit windows 8.1 version ( from the system requirements pdf), if you have installed it in 32 bit machine, that would have created the problem.
you can create a net "NOT_CONNECTED" with the desired pin and another NC Pin, and assign rules to this net.
you need not to route this net and it will be ignored by verify design rules as well.
Thanks for the reply Chris. This error happens during SPICE netlist generation. There is very little to indicate what is wrong.
"Internal error".
I was hoping that someone could read the TechNote and provide some clues.
Thanks,
Terry
Klaus,
The scripts posted by myself and Jeremy Parker only work on DX/Expedition libraries and designs. We don't have anything for PADS Logic/PADS.
Sorry,
Scott
Hello,
In this case for one pin of the component you will have to ignore missing connection due to the non-plated hole. In two or multi layer designs system consider every through pin as plated and if it is missing, reporting connectivity issue. If the design were a single sided board, PADS can deal with the none plated pins by declaring in Layer Definition that it is a single sided design.
Regards, Yan
Hi,
I had an issue with VeSys harness that I was able to solve using the "Batch Update Library Parts" action which can be accessed by selecting “Actions>Update>Batch Update Library Parts" from the top toolbar. I now have a few questions about this action.
My issue was that at one point, I had made a change to the acceptable wire size for a couple of terminals in the component library, but I recently realized that this change is not being reflected in some of my designs. For these designs, when I run the "Select Cavity Components" process, it doesn't match the current information that is in the component library. The terminals are being selected as if I had not made the changes to the component library. I tried selecting "File > Refresh > Refresh All" from the top toolbar, but VeSys was still selecting the wrong terminals. I then tried the “Batch Update Library Parts” action and it fixed the issue that I have.
I should mention that I am working on VeSys harness designs with 2 different databases, and I regularly transfer designs between the two databases. I transfer library component information between the two databases as well, and I was suspecting that this might be the cause of my issue.
I was wondering what does the “Batch Update Library Parts” action do exactly and how is it different from the “Refresh All” process?
Should I be performing this action every time I make a change to the library, or whenever I transfer information between databases?
Should I be performing this action for every harness design or does doing it once apply the changes everywhere?
Thank you
First the property needs to be definied in the property file, use Tools, Property Definition Editor to review the properties allowed in a design.
Then you may find this video useful... DxDesigner 8 -Page Numbers and Border Properties-EE7.9.3
Thankyou for that. I assume though that there is only one special "NOT_CONNECTED" net so this method will really only work for pins with the same rules?