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Manage Central Library in xDxDesigner with Integrated flow

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Hello Everyone,

 

I recently switched to integrated flow with the xDxDesigner and Pads Layout  (VX1.1). The integrated flow indeed provides lots of convenience

by centrally manage all symbols, decals and parts in a common library. It is also very nice to have the constraint manager to set all rules and quickly

create differential pairs. However, it does take more time to get familiar with the management of the library: import symbols, decals; manage partition;

update symbols and decals within the library and inside individual design. I am currently having some troubles with the following several tasks. I 

wonder if anyone would be helpful to give some hints

 

1.  Import individual decal: it seems to be easy to import individual logic symbol using the "xDM library tools". How should I import individual

decal file (xxx.d) to one of the partitions in the central library? Right now, I can only use  "Central Library Migrator" to import a whole bunch of

decals. But that also creates a new partition and all parts and symbols are also imported. 

 

2. Remove association of decals with parts:  As can be seen in the follow snapshot of the central library. There are two decals 

associated with the same parts. Since they are identical, I wanted to remove the association of one duplicate then delete the duplicated

decal to avoid confusion. However, this is not possible without deleting the part.  Any hint to work around this problem since I have lots

of parts with similar situations to work with.

 

 

3. Delete multiple symbols and parts. Right now, I have to right click on each symbol to delete it. If I have many unused, obsolete

parts, symbols, decals to be removed. Any way to select all of them and delete them at once?

 

4. Update Decals in the central library. Sometimes, I would like to modify decals using the "xDM library tools" and then would like to

propagate to the PCB layout. propagate the change to the PCB layout. However, I do not find any option in the PADS layout tool to"update decal from the library".

I guess this has something to do with the update of the local library. I went to "Setup"-->"Project Integration"  and tried to rebuild the local library.

It usually does not work out of the way. Sometimes even broke the connectivity and requires repackaging of many parts. The workaround

I have used is to delete the old part and create a brand new part with the modified decal and a different part name. I wonder what is the easiest

way of propagating changes between the central library and the layout within one PCB project. 

 

Sorry for these lengthy questions. However, I do believe any discussion on these issues will save a significant amount of time for many others who

moved to integrated flow.

Thanks!

Liang


PADS 3D, custom attribute in silkscreen layer

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Hi,

I tried the PADS 3D function with PADS VX.2.

I have a part with an attribute: "Part Number" and it value is on the silkscreen layer.

Now the PADS 3D view doesn't show this attribute value.

If I change it to Ref.Des it will show the value.

 

Is there a way to add "custom" attributes for the PADS 3D view?

 

2D View:

10045555: Part Number

10,5: Value

pcb_2d.png

3D View:

Part Number & Value is missing

 

pcb_3d.png

 

CAM settings:

cam.png

 

Only the Attributes listed in the summary will be shown in 3D.

 

How to add "Part Number", "Value",....

Re: Hyperlynx differential impedance calculation mistake

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Hello!

I have noticed that you selected, in Saturn PCB, ”Edge Coupled Ext” for the Differential Layer option. This would be valid if the differential pair was on an external layer.

If you select ”Edge Cpld Int Asym” you get 80,497 Ohm, which is very close to what HyperLynx calculates.

 

Saturn 6.89.png

 

Best regards,

 

Mircea Slanina

Re: Hyperlynx differential impedance calculation mistake

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Dear fiend Mircea Slanina, thank you for your attention and response !

You are right, my Saturn stackup model was wrong.

I looked on this as on Microstip, because it is Flexible PCB where the flexible area actually has only 2 layers, and it is major area. So, it seems, Hyperlynx doesn't support Rigid Flexible PCBs with different stackups over the same PCB. Or, just the exporting process from Altium to Hyperlynx doesn't support it.

 

But anyway, there is still significant mismatching between Saturn and Hypelynx diff impedance calculations .

In case you are showing,  H2 layer is 5mil .

In my case , the H2 of Saturn means the dielectric row2 (DE_Top_Layer)  in my stack-up, which is 25.2 mil .

Here is correct Saturn model, and I still expecting from Hyperlynx to get the same result . So, as before, I still missing here anything.

3.JPG

Hyperlynx differential impedance calculation mistake

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!Hi,

I'm simulating an exported from Altium designer 16.1 Rigid Flex PCB board, which contains suppose to be 100 ohm diff pairs  . The Hyperlink calculates its Zdiff as 82 ohm for some reason .

1. The designed PCB with correct PCB stack-up and Diff pare parameters where set in the Altium .

2. Exported as HYP file from Altium and opened in Hyperlynx V9.4 .  All passed well, with correct traces drawing and layers stack-up . The ref / signal planes were selected .

3. The selected diff traces where extracted from BoardSim to LineSim , in order to review a transmission lines topology and impedance.

Somehow, the calculated by Hyperlynx differential embedded microistrip impedance is 82.1 ohm, while it suppose to be 100 ohm according to its layers stack-up and Er.

Attachment 1.jpg - screen of LineSim with all the related  geometric parameters of transmission line with a wrong calculated Zdiff.

Attachment 2.jpg - the correct calculated Zdiff by two known impedance calculators using the same trace and stack-up parameters.

Where is my mistake ?

Linking Different Standard Reference Schematic to Single Schematic

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Hello All ,

 

We are using PADS 9.2 and we want to link different schematic to single schematic . Is it possible ?

 

Suppose we have a standard reference schematic for every circuit diagram with the standard naming convention .

We want to recall these standard schematic every time and want to link all such schematic to one single schematic while undergoing new design .

 

Is it possible ?

 

Please assist .

 

Best Regards ,

Parth Sutariya

Hardware CAD Engineer

MATRIX COMSEC

Vadodara , Gujarat

INDIA

Clearance between Signals

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Hello All ,

 

I have a doubt regarding clearance between different single ended signals .

 

Right now we are keeping the same clearance between the traces as that of the signal trace width .

 

For Example .

 

For Single ended signal , suppose I am routing the signal with the trace width of 8 mils keeping clearance of 8 mils between other single ended signal.

Can I reduce the clearance less than 8 mils ?

 

Does it invite cross talk between signals considering both high frequency and low frequency signals ?

 

Please assist .

 

Best Regards ,

Parth Sutariya

Hardware CAD Engineer

MATRIX COMSEC

Vadodara , Gujarat

INDIA

Re: Clearance between Signals

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Hello Parth, I've moved your question to the HyperLynx SI community for a quicker response. Best regards, Cathy


How do I "overlap" vias with testpoints.

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The testpoints are only on the bottom side.  The company does not want to use vias for testpoints, nor do they want to have a trace go from a via to a test point (antennas).  I have been instructed to have the edge of my test point be adjacent to the via hole (not the pad).  How do I set a zero clearance for vias and test points?  The via is either sucked to the center of the testpoint or I get immovable metal object errors.

Re: How do I "overlap" vias with testpoints.

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I haven't tried any of this, but it is an idea that I think may resolve your problem.

1st Define your test point pad as an oval shape with an offset origin (similar to sketch included)

2nd Then on your design if you place this oval test pad onto a via, it will locate at the cell origin.

Via will be attached to the test pad with no track and can be probed onto left hand side of test pad - so not as to probe direct onto a via.

Re: COVER FREE AREA

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   Hi Matthew

 

thanks for your support

Unfortunately doesn't work correctly how I need in my gds file:

 

2016-10-11_181858.jpg

2016-10-11_182002.jpg

 

2016-10-11_182028.jpg

In my hierarchy.

Layer 997 is like your 3

Layer 998 is like your 4

Layer 999 is like your 50

 

In my example

the layer 997 is present only on cell MPW_SL

the layer 998 is present on both cells MPW and MPW_SL

 

After

$Lnew NOT 998 997 999

the layer 999 has been created WRONG on both cells MPW and MPW_SL

 

I need that correct layer 999 will be present only on cell MPW_SL

Is possible do it?

 

   Many thanks

    Luciano

Re: COVER FREE AREA

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Hey Luciano,

 

Without knowing exactly what you want, I tried to come up with something that demonstrates a number of options for you. Run this script in DESIGNrev to see the output. I think it will be more clear if you play around with turning on and off the layers. I put temporary and output layers on the same base layer but with different datatypes to help visualize the problem. The script does this:

1. Creates an example layout with two cells instantiated in a topcell.

1.png

The two cells have different geometry on layer 3.

2.png

2. Creates temporary layers (tmp1 and tmp2) in both cells that covers each cell entirely.

3.png

3. Creates a temporary layer (tmp3) that covers the entire top cell.

4.png

3. ORs the two cell layers onto a new temporary layer (tmp4) with the hier flag on so it propagates up to the top cell.

4. NOTs the combined tmp4 layer with the tmp3 layer to generate a layer (top_output_outlines) that entirely surrounds the cells.

5.png

 

This green layer might be what you're looking for. If you're also looking to generate a layer that surrounds the geometry inside the cells, I've added a few more operations to the script that do that:

 

5. Temporary layers in Step 2 are NOT'd with the design layer and OR'd together to get a layer (tmp5) that covers the empty space in each cell.

6.png

6. The new layer is NOT'd with the temporary layer (tmp3) that covers the entire top cell. This produces a layer that surrounds the design as if it was flat.

7.png

The cellC_output and cellB_output layers are just the NOT of the geometry in each cell.

 

There are plenty of ways to do this, so I'm sure someone could come up with a different solution.

 

Here's the script (just copy and paste it into a text file and call calibredrv myScript.tcl):

 

##############################################################################

# BEGIN

##############################################################################

#create new layout

set ll [layout create]

 

#====variables=======

#cell names

set topcell TOP_CELL

set cellA cell_A

set cellB cell_B

 

set design_layer 3

#temp layers

set tmp_layer1 5.1

set tmp_layer2 5.2

set tmp_layer3 5.3

set tmp_layer4 5.4

set tmp_layer5 5.5

#generated overlay layer

set outlayer1 50.1

set outlayer2 50.2

set outlayer3 50.3

set outlayer4 50.4

#====/variables=======

 

##########################################################

# This part creates a layout with 2 cells for the example

##########################################################

#create new topcell

$ll create cell $topcell

 

 

#create layers in layout

$ll create layer $design_layer

$ll create layer $tmp_layer1

$ll create layer $tmp_layer2

$ll create layer $tmp_layer3

$ll create layer $tmp_layer4

$ll create layer $tmp_layer5

$ll create layer $outlayer1

$ll create layer $outlayer2

$ll create layer $outlayer3

$ll create layer $outlayer4

 

#create child cells

$ll create cell $cellA

$ll create cell $cellB

 

#create some random shapes for cellA

$ll create polygon $cellA $design_layer 10 10 100 100

$ll create polygon $cellA $design_layer 120 200 200 100

$ll create polygon $cellA $design_layer 140 50 300 10

 

#create some random shapes for cellB

$ll create polygon $cellB $design_layer 5 50 95 95

$ll create polygon $cellB $design_layer 0 0 100 10

$ll create polygon $cellB $design_layer 0 20 100 30

 

#Place the cells as an instances in the topcell

set x 0

set y 0

set mirror 0

set angle 0

set mag 1

$ll create ref $topcell $cellA $x $y $mirror $angle $mag

set x 250

set y 250

set mag 2

$ll create ref $topcell $cellB $x $y $mirror $angle $mag

 

##########################################################

# Here's where the layer merging and NOTing takes place

##########################################################

#get the bounding box of each cell instance and the top cell

set cellCoordsA [$ll bbox $cellA]

set cellCoordsB [$ll bbox $cellB]

set cellCoordsT [$ll bbox $topcell]

 

#create a new layer the same size as the bounding box over each cell

eval $ll create polygon $cellA $tmp_layer1 $cellCoordsA

eval $ll create polygon $cellB $tmp_layer2 $cellCoordsB

eval $ll create polygon $topcell $tmp_layer3 $cellCoordsT

 

#Perform a NOT between the random shapes and the blanket temporary layer to get the difference layer

$ll NOT $tmp_layer1 $design_layer $outlayer1

$ll NOT $tmp_layer2 $design_layer $outlayer2

 

#process top layer (different ways to do this depending on what you want

$ll OR $tmp_layer1 $tmp_layer2 $tmp_layer4 -hier 1

$ll NOT $tmp_layer3 $tmp_layer4 $outlayer3

 

#create combinedlayer that considers hierachy of CellA and B blockages

$ll OR $outlayer2 $outlayer1 $tmp_layer5 -hier 1

$ll OR $outlayer3 $tmp_layer5 $outlayer4 -hier 1

 

#rename layers for readability in OASIS

$ll layernames $outlayer4 top_output_combined

$ll layernames $outlayer3 top_output_outlines

$ll layernames $outlayer2 cellB_output

$ll layernames $outlayer1 cellC_output

$ll layernames $design_layer design

$ll layernames $tmp_layer1 tmp1

$ll layernames $tmp_layer2 tmp2

$ll layernames $tmp_layer3 tmp3

$ll layernames $tmp_layer4 tmp4

$ll layernames $tmp_layer5 tmp5

 

#create the OASIS file

$ll oasisout output.oas

Re: How to export a complete net from layout which was found by Calibre LVS finder?

Re: How do I "overlap" vias with testpoints.

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You can allow vias under the pad in the editor control but you should create a unique pad in the padstackeditor for testpoints just in case same pad is used on SMD components to avoid accidental vias in them. (can also place a via obstruct in center on the cell)


Though for some reason it does not allow to place the testpoint with an offset on the vias but it does work if you place the testpad next to the via, route a trace and then move the testpoint onto the via... (or place with drc off)

 

Working with offset pads seems a bit dicy because the testpoint center to center will not be chekced properly when using different rotations and not sure if all downstream tooling will use pad center and not testpoint part coordinates.

Re: Database for DxDatabook

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We use a defined workflow for part creation. Everyone has access to the database but noone is allowed to alter the database alone.


Re: Manage Central Library in xDxDesigner with Integrated flow

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Hi Liang,

I can help with a couple of your questions.  2 and 3 are maybe's...

 

1.) Open 2 layouts, layout 1 should have the decal you want to move to your central library, layout 2 should be tied to a project that uses your central library.  Place layout 2 in eco mode, in layout 1 highlight your decal, right click and copy the decal, in layout 2 paste the decal into the layout.  In layout 2 right click on the decal and click save to library and you will be prompted to save the part and the decal and be able to choose which partitions each of them should go to.  You can also skip importing the part and only import the decal if that is all you need.

 

2.) Do this at your own risk try this on a backup of your library first!  Inside of the central library there is a folder called PADSLibs which contains all of your library partitions in a Pads Logic netlist flow format.  You can open Pads layout in netlist flow select File > Library... and map those libraries and edit them deleting the extra decals.  Next, delete the SysIndex.cbf file from your central library folder, open a project that uses your central library and open xDM Library Tools, your library should start re-indexing itself.  Once that is finished if everything goes ok your parts should list only the decal that remains.

 

3.) Basically the same method as 2, the only difference is that any xDx symbols you want to delete can be done directly through Windows Explorer in your SymbolLibs folder within your central library.

 

4.) In your layout right click on the decal you want to update and Edit Decal, once the decal is open in the decal editor click on File > Open Decal, you will get a prompt asking if you are sure that you want to discard the decal loaded from the board, click yes.  You can then browse for the updated library version of your decal, click ok then close the decal editor, layout will ask if you want to replace just the selected decal or all parts that use that decal, replace them all and you should be good to go.

 

-Travis

Re: COVER FREE AREA

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Hi Mattew,

 

I'll try explain You better.

 

This is my scrpt

 

I need that on layer 999.1 will be present the NOT of layer 997 only on cell MPW_SL

 

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

#######

 

 

# Load file.gds

 

 

array set peekdata [layout peek file1.gds.gz -type -topcell -layers -units]

puts "TOPCELL: $peekdata(topcell)"

 

 

set format [string toupper $peekdata(type)]

puts $format

 

 

set Lone [layout create file1.gds.gz -dt_expand -preservePaths -preserveProperties -preserveTextAttributes]

set precision [expr int (1/([$Lone units]))]

$Lone units microns $precision

foreach mych [$Lone children $peekdata(topcell)] {

    puts "STRUCT: $mych \n"

    foreach pp [$Lone children $mych] {

    puts "$pp \n"

    }        

    }

   

puts $peekdata(layers)

 

 

set mychx1 [exec echo $peekdata(topcell) | sed {s/_TOP/ /g} | awk {{print $1}}]

 

puts $mychx1

 

set mychx2 [exec echo ${mychx1}_SL]

puts $mychx2

 

set bboxlo [$Lone bbox $peekdata(topcell)]

puts $bboxlo

 

 

puts $peekdata(units)

 

################### rename cells on hierarchy #######################

 

set suff   [clock seconds]

 

set norename ""

foreach mytops [$Lone topcell all] {

  set norename "$norename $mytops "

  foreach mychild [$Lone children $mytops] {

  set norename "$norename $mychild "

  }

  }

 

foreach mycell [$Lone cells] {

  if { [string first  $mycell $norename] == -1} {

  set newcell  "${mycell}_${suff}"

  puts "Renaming $mycell to $newcell"

  $Lone cellname $mycell $newcell

  } else {

  puts "Cell name $mycell unchanged"

  }

 

}

 

$Lone create layer 997

$Lone create layer 999.1

$Lone create polygon $mychx2 997 [lindex [$Lone bbox $peekdata(topcell)] 0] [lindex [$Lone bbox $peekdata(topcell)] 1] [lindex [$Lone bbox $peekdata(topcell)] 2] [lindex [$Lone bbox $peekdata(topcell)] 3]

 

################# create temporary gds file starting from both cells ###########################################

 

  if { $format == "GDS" } {

 

 

$Lone gdsout $mychx1.gds.gz $mychx1

set Lonet1 [layout create $mychx1.gds.gz -dt_expand -preservePaths -preserveProperties -preserveTextAttributes]

 

 

$Lone gdsout $mychx2.gds.gz $mychx2

set Lonet2 [layout create $mychx2.gds.gz -dt_expand -preservePaths -preserveProperties -preserveTextAttributes]

 

 

       # $Lone gdsout file1.gds.gz

   } else {

      #  $Lone oasisout file1.oas -cBlocks -strictMode

   }

 

   

# set mychx1 [lindex [$Lone children $peekdata(topcell)] 0]

# set mychx2 [lindex [$Lone children $peekdata(topcell)] 1]

   

 

 

##########################

 

array set peekdata2 [layout peek file2.gds.gz -type -topcell -layers -units]

puts "TOPCELL: $peekdata2(topcell)"

 

 

set format2 [string toupper $peekdata2(type)]

puts $format2

 

 

set Ltwo [layout create file2.gds.gz -dt_expand -preservePaths -preserveProperties -preserveTextAttributes]

set precision2 [expr int (1/([$Ltwo units]))]

$Ltwo units microns $precision2

foreach mych2 [$Ltwo children $peekdata2(topcell)] {

    puts "STRUCT: $mych2 \n"

    foreach pp2 [$Ltwo children $mych2] {

    puts "$pp2 \n"

    }        

    }

   

puts $peekdata2(layers)

 

 

set mychy1 [exec echo $peekdata2(topcell) | sed {s/_TOP/ /g} | awk {{print $1}}]

 

puts $mychy1

 

set mychy2 [exec echo ${mychy1}_SL]

puts $mychy2

 

set bboxlo2 [$Ltwo bbox $peekdata2(topcell)]

puts $bboxlo2

 

 

puts $peekdata2(units)

 

################### rename cells on hierarchy #######################

 

 

set suff2   [clock seconds]

 

set norename2 ""

foreach mytops2 [$Ltwo topcell all] {

  set norename2 "$norename2 $mytops2 "

  foreach mychild2 [$Ltwo children $mytops2] {

  set norename2 "$norename2 $mychild2 "

  }

  }

 

foreach mycell2 [$Ltwo cells] {

  if { [string first  $mycell2 $norename2] == -1} {

  set newcell2  "${mycell2}_${suff2}"

  puts "Renaming $mycell2 to $newcell2"

  $Ltwo cellname $mycell2 $newcell2

  } else {

  puts "Cell name $mycell2 unchanged"

  }

 

}

 

 

$Ltwo create layer 997

$Ltwo create layer 999.1

$Ltwo create polygon $mychy2 997 [lindex [$Ltwo bbox $peekdata2(topcell)] 0] [lindex [$Ltwo bbox $peekdata2(topcell)] 1] [lindex [$Ltwo bbox $peekdata2(topcell)] 2] [lindex [$Ltwo bbox $peekdata2(topcell)] 3]

 

 

################# create temporary gds file from bosth cells ###########################################

 

 

if { $format2 == "GDS" } {

 

 

$Ltwo gdsout $mychy1.gds.gz $mychy1

set Ltwot1 [layout create $mychy1.gds.gz -dt_expand -preservePaths -preserveProperties -preserveTextAttributes]

 

 

$Ltwo gdsout $mychy2.gds.gz $mychy2

set Ltwot2 [layout create $mychy2.gds.gz -dt_expand -preservePaths -preserveProperties -preserveTextAttributes]

 

 

      #  $Ltwo gdsout file2.gds.gz

        } else {

      #  $Ltwo oasisout file3.oas -cBlocks -strictMode

        }

   

##############################

 

 

array set peekdata3 [layout peek file3.gds.gz -type -topcell -layers -units]

puts "TOPCELL: $peekdata3(topcell)"

 

 

set format3 [string toupper $peekdata3(type)]

puts $format3

 

 

set Lthree [layout create file3.gds.gz -dt_expand -preservePaths -preserveProperties -preserveTextAttributes]

set precision3 [expr int (1/([$Lthree units]))]

$Lthree units microns $precision3

foreach mych3 [$Lthree children $peekdata3(topcell)] {

    puts "STRUCT: $mych3 \n"

    foreach pp3 [$Lthree children $mych3] {

    puts "$pp3 \n"

    }        

    }

   

puts $peekdata3(layers)

 

 

set mychz1 [exec echo $peekdata3(topcell) | sed {s/_TOP/ /g} | awk {{print $1}}]

 

puts $mychz1

 

set mychz2 [exec echo ${mychz1}_SL]

puts $mychz2

 

set bboxlo3 [$Lthree bbox $peekdata3(topcell)]

puts $bboxlo3

 

 

puts $peekdata3(units)

 

################### rename cells on hierarchy #######################

 

 

set suff3   [clock seconds]

 

set norename3 ""

foreach mytops3 [$Lthree topcell all] {

  set norename3 "$norename3 $mytops3 "

  foreach mychild3 [$Lthree children $mytops3] {

  set norename3 "$norename3 $mychild3 "

  }

  }

 

foreach mycell3 [$Lthree cells] {

  if { [string first  $mycell3 $norename3] == -1} {

  set newcell3  "${mycell3}_${suff3}"

  puts "Renaming $mycell3 to $newcell3"

  $Lthree cellname $mycell3 $newcell3

  } else {

  puts "Cell name $mycell3 unchanged"

  }

 

}

 

 

$Lthree create layer 997

$Lthree create layer 999.1

$Lthree create polygon $mychz2 997 [lindex [$Lthree bbox $peekdata3(topcell)] 0] [lindex [$Lthree bbox $peekdata3(topcell)] 1] [lindex [$Lthree bbox $peekdata3(topcell)] 2] [lindex [$Lthree bbox $peekdata3(topcell)] 3]

 

 

################# create temporary cells for both cells ###########################################

 

 

if { $format3 == "GDS" } {

 

$Lthree gdsout $mychz1.gds.gz $mychz1

set Lthreet1 [layout create $mychz1.gds.gz -dt_expand -preservePaths -preserveProperties -preserveTextAttributes]

 

 

$Lthree gdsout $mychz2.gds.gz $mychz2

set Lthreet2 [layout create $mychz2.gds.gz -dt_expand -preservePaths -preserveProperties -preserveTextAttributes]

 

 

       # $Ltwo gdsout file3.gds.gz

        } else {

       # $Ltwo oasisout file3.oas -cBlocks -strictMode

        }     

   

###########################################################################################################   

 

 

# Create empty cell

set Lnew [layout create]

 

 

# Create new topcell and children cells for new layout

$Lnew create cell MPW_TOP

$Lnew create cell MPW

$Lnew create cell MPW_SL

 

 

$Lnew create ref MPW_TOP MPW 0 0 0 0 1

$Lnew create ref MPW_TOP MPW_SL 0 0 0 0 1

 

 

# Copy patterns on new layout

$Lnew import layout $Lonet1 TRUE overwrite

$Lnew import layout $Lonet2 TRUE overwrite

$Lnew import layout $Ltwot1 TRUE overwrite

$Lnew import layout $Ltwot2 TRUE overwrite

$Lnew import layout $Lthreet1 TRUE overwrite

$Lnew import layout $Lthreet2 TRUE overwrite

 

 

 

 

$Lnew create ref MPW "${mychx1}" -4546500 -3282500 0 0 1

$Lnew create ref MPW_SL "${mychx2}" -4546500 -3282500 0 0 1

 

$Lnew create ref MPW "${mychx1}" -4546500 -4882500 0 0 1

$Lnew create ref MPW_SL "${mychx2}" -4546500 -4882500 0 0 1

 

$Lnew create ref MPW "${mychy1}" 0 3743500 0 0 1

$Lnew create ref MPW_SL "${mychy2}" 0 3743500 0 0 1

 

$Lnew create ref MPW "${mychz1}" 4358500 -3366500 0 0 1

$Lnew create ref MPW_SL "${mychz2}" 4358500 -3366500 0 0 1

 

$Lnew create layer 998.1

$Lnew create layer 998.2

 

$Lnew create polygon MPW 998.1 [lindex -6567500] [lindex -8367500] [lindex 6567500] [lindex 8367500]

$Lnew create polygon MPW_SL 998.2 [lindex -6567500] [lindex -8367500] [lindex 6567500] [lindex 8367500]

 

 

$Lnew NOT 998.2 997 999.1

 

 

# Create final oasis file

$Lnew oasisout MPW_MULTI.oas

 

array set peekdatao [layout peek MPW_MULTI.oas -type -precision -topcell -topcells -layers]

puts $peekdatao(layers)

 

exec rm $mychx1.gds.gz $mychx2.gds.gz $mychy1.gds.gz $mychy2.gds.gz $mychz1.gds.gz $mychz2.gds.gz

Re: Load Color Scheme in DxDesigner

Re: Manage Central Library in xDxDesigner with Integrated flow

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Hello Travis,

Thanks a lot for sharing the trick! 

Regarding your reply to my first question, that's exact what I figured out as a walk around: work reversely from

pad layout instead of from the central library. I like the idea of central library management. However, it seems to me,

 

I like the idea of central library management. However, it seems to me, the current central library acts more or less like a symbolic link system holding all the parts, symbol, decal information in one place while the real decal and symbol files are still scattered around into a few folders. These symbol files even copied to the local project directory. This is sometimes confusing when one updates from various places (project schematic, layout or central library manager). My personal's opinion is that it would be more convenient for the central library manager to take a higher level of control of everything so that one only needs to deal with it for any update, copy, delete and modification rather than looking at different places.

 

I have just tried out the fourth trick you provided and that is neat! I will post my findings later after I have tried with the solution for  2),3).

Thanks!

Liang

Re: Capital launcher question

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Let me chime in here that the users at Cirrus all work in both Logic and HarnessXC.  We would love to be able to access one from the other.  And it appears that the Trace command in v2015 helps in that direction.  But I still don't like how Logic and HarnessXC just say basically "you can't do that" if a user tries to open a Logic design from HarnessXC or a HarnessXC design from Logic.  It would be better if the message said exactly what program you need to use for that design, and better yet if it offered to open the design in the appropriate tool for you.

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