Thanks, David
I tested your command,but I cannot monito dmscapacuser.
I can monitor the next command
lmutil lmstat -f dmscapusr100
However, It is not what I expect.
I will discuss with Mentor Japan about this problem.
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Re: How can I monitor capacity-license
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Why redundant wires generated in integrator design?
Hi:
we found redundant wires generated while customer implement engineers changes in capital integrator, customers changed some options configuration and we thought that changes didn't affect these redundant wires.
1:customer found redundant wires as below, another wire generated after CWS and two wires with the same connectivity.
2:but we try to delete wires and process CWS again, only 4 wires generated, this is the result customer expected
The questions is why redundant wires generated in capital integrator, we are been anxious about how many these redundant wires generated in the whole integrator plane, we need find these wires and avoid this issues.
Regards
Denglong
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symbol library for new line style
Hello,
Can anyone tell me how can i link existing symbol library with New line style.
I just created a new line style but the connector symbols are not visible in that Line Style, but connector symbols are visible when i change the line style.
Regards,
Neelu Sharma.
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Re: Why redundant wires generated in integrator design?
CWS should definitely not generate redundant wires - this is not something we are aware of. It is clear that just running CWS from scratch doesn’t create them, so to understand why redundant wires were generated, it would be interesting to understand the exact process you have been using.
The design rule check “Redundant wires” will answer your concern and list down any redundant wires present in an Integrator design
Regards
Abhishek Gupta
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Re: Why redundant wires generated in integrator design?
Hello Denglong,
Good day.
I just have some confirmation,
1. Are there any double signal with different option expression in Capital Logic, that is executed after amending option configuration?
If this is not the cause, can we create a SR to investigate the issue?
Thanks and best regards,
Dan
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Re: Why redundant wires generated in integrator design?
Thanks Abhishek:
The DRC can list all redundant wires for customer to check the data.
we have tested how the redundant wires generated based on initial data ( customer created revision from old data), so the initial signal generated 4 wires with part number, the first step we process CWS，then we found 2 wires generated without part number. we check the options and compare with other initial wires, they have the same options expression. the second step we delete all wires related the signal, we process CWS again, only 4 new wires generated without part number.
So we are confused, we want to know how the redundant wires generated in this case.
Regards
Denglong
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Re: Why redundant wires generated in integrator design?
Thanks Dan:
In this case, only one signal defined in capital logic, not double signal. and i'm afraid we can't create SR for customer currently
Regards
Denglong
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Why is it not possible to change Pad Entery Rule in the Library
Like the Title says anyone knows why it is not possible to change the Pad entry Rule in the Library?
On every Design i have to deal with this Pad Entry rule more than once. Sometimes it seems to reset back and sometimes not.
Am i the only one having issues with that? How are you dealing with this?
Also i have no clue where the Default is defined if i press reset to Default, not all Pads reset to the same settings, as you can see some allow side entry and some not.
Is the Default entry somehow determined by the tool? Maybe depending on the position of the pad or the Pad Origin...
Maybe Automation is the only solution for this...
BR RALF
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Re: Why redundant wires generated in integrator design?
Hi Denglong,
The process is still not completely clear to me. You say you started with 4 wires (I assume this is the 'correct' result). Then you say "we found 2 wires generated without part number" - was this as a result of running CWS again? If so, does that mean that after you deleted all the wires and ran CWS to get the 'correct' result, if you run CWS again it will add the two extra wires?
In other words, do these steps result in the 'wrong' result?
1. Delete all wires for signal
2. Run CWS - get correct result
3. Run CWS again - get wrong result?
Thanks,
Simon
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Re: Variant Manager excel report from script
I am trying to use this to import variants into Xpedition. When I open the script in Xpedition and select the Import option I get an error: "Object doesn't support this property or method : dxdApp.GetProjectData". Does this script not work in Xpedition?
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Re: Pointing Xpedition projects to .IPL files not in Mentor Project/Program Paths
Yes this worked. Thank you both.
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Add Special Characters to "Add Text"
Dear Factory,
In many cases the requirement to add some kind of Note (Flag Note) is a Harness Drawings is almost mandatory.
I many cases the ability to add Special Characters is required: Such as:
±
I can copy and paste from MS Word into Add Text
Is it possible to add these special characters into the Add Text GUI?
This will really help use with maintianing our tool with drafting standards.
In addition:
It is a Requirement that a leader line be a part of a Bubble, BOM ID note.
Therefore our System with Bubble does not meet ASME Y14.41 and ASME Y14.100 drafting standards.
Best regards,
Rodney
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Re: Add Special Characters to "Add Text"
HI Rodney
You can do that today using ALT keyboard sequences. Capital text editor simply takes input from the keyboard so if you enter a special character sequence it will take it, no problem.
Example here below where I used the ALT 241 sequence to get the ± symbol
For a handy list of special character commands, see the following page:
Special Characters — Alt Keyboard Sequences
Thanks
Muhammad
P.S. You need to use the number pad for this to work!
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Re: Add Special Characters to "Add Text"
Hello Muhammed.
Unfortunately that does work when your keyboard does not have the numeric keypad.
Many new laptop, omit this part of the keypad. This is why I am asking to have the ASCII symbols “special characters” added.
I guess I could buy a USB Numeric Keypad.
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Re: Add Special Characters to "Add Text"
In my experience when the numpad is ommited a special key (Fn) usually enables an overlain keypad on top of existing letter keys. But in any case, I see your point.
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PADS 9.5 re-install
My PADS 9.5 quit working and the files were deleted. I'm trying to reinstall 9.5.
When it gets to the part where the MGC SDD Configurator is "Registering wg files..." i get the message box"C:\MentorGraphics\win32\sdd_register.exe" that says: "Cant Find C:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\lib\CommandBarSvr75.dll" But that file exists in that directory. If I click ok it says it can't find another file, etc...
I am running Win 7 Enterprise 64 bit.
Any suggestions?
My IT dept wants to wipe my hard drive. I've told them no way, there are way to many programs I would need to reinstall / configure.
Thanks in advance,
Greg
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Re: PROBLEM DURING MERGING GDS FILES
Hi Luciano,
Do your three source layouts have any top-level geometry? The $L create cell command does not copy the placements as per the Calibre DESIGNrev Reference manual:
"Creates a new cell with the given name. ... and then copies all geometry (no placements are copied) into the cell."
I created a small test case with your script and it did create geometry from the individual layouts in the output, but only top-level geometry and your new cell references. If your layouts do not have top-level geometry, the output GDS appears with hierarchy, but no contents in the cell references. Perhaps that's what you're seeing?
regards,
matt
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Re: PROBLEM DURING MERGING GDS FILES
I have attached my test case with some layouts if you haven't already solved the issue. I modified your script to use $L import layout instead of $L create cell. I then read and renamed the top cells to your original values and used $Layout create ref to place them. All the geometry comes through in this version.
thanks,
matt
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Re: PROBLEM ON Layout Hierarchy EXCTRACTION
Hi,
It sounds like a file IO issue. The script works for me. I would check to make sure these lines have the correct permissions and paths to the files:
set fileID [open dump_hier.txt w]
#
# Step 1: open the layout
#
set layout [layout create std_.gds]
You can try the attached testcase and see if that works for you.
regards,
matt
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Re: Why redundant wires generated in integrator design?
Hi Simon:
The initial 4 wires is correct result, we think there would no changes for these wires if we run CWS, but the result is unexpected, another 2 wires generated after CWS, But when we delete all wires for the signal then we run CWS again, the result is correct, we tested the steps you pointed
1:delete 4 wires for the signal
2:Run CWS- get correct result, 4 wires generated
3:Run CWS again-no changes for the 4 wires, correct result
Regards
Denglong
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