Last chance to submit a design to the Technology Leadership Awards
Hey everybody, Just wanted to send out a reminder that tomorrow is the deadline for submissions to the TLAs. If you need a bit of help filling out a last-minute application, be sure to check out...
View ArticleRe: license installation problem
Dear David,Thanks for your quick reply in my question. First of all, the status I saw it was in the license server machine. I've read your answer and applied all the suggestions you gave me , but the...
View Articleautomation: DxDesigner connect to different Central Library
I have a design with outdated central library path information. I have found that... dim oProjectData : Set oProjectData = Application.GetProjectDataoProjectData.CentralLibraryPath = "path to lmc" ......
View ArticleRe: Catia V6 ixf implementation
Hi - this feature is available in VeSys 2.0 2014.1 SP1510
View ArticleHow to get visible drill holes on layout?
Hi. I have designed PCB with PADS layout (ver. 9.5).I want to print layout on transparent sheet for light exposure.Etching and drilling will be done manually so I need visible holes on each pads, vias,...
View ArticleRe: How to get visible drill holes on layout?
Hello Tuomo, This an interesting situation. You can partly solve Copper Pour issue by changing Flood Over parameter to Thermal Connections, however doing this will not solve the problem of the trace...
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Font size for Modelsim ASE 10.1d on linux
Hi,I'm using Modelsim ASE 10.1d on linux (Lubuntu) and the font size is too small (I'm visually impaired and I have problems to read) but I can't make it bigger. Do you know what I could try?Thanks.
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How do I create an associated net so I can create a matched length group for...
I have a design where a bus of signals pass through a isolator and SSR to a connector. We want to eliminate any skew not associated with the isolator. Currently we set up each section...
View ArticleRe: How do I create an associated net so I can create a matched length group...
I had the same problem once. My problem was, that associated nets have some limitations with non discrete devices. If you want something like a solid state relay, you have to define the several lines...
View ArticleRe: How do I create an associated net so I can create a matched length group...
This design is in netlist flow. I'm familiar with setting up gates in the integrated flow, but I'm not sure how to do it in the netlist flow.
View ArticleRe: How do I create an associated net so I can create a matched length group...
Ok, i am working with DxDesigner as Schematic tool, you too i think.I think you can setup your gates with the parts property. They must have one single input and output. So you have an relay symbol,...
View ArticleRe: How do I create an associated net so I can create a matched length group...
That sounds reasonable ... I'll have to find some time to set this up and try it out. I've also used the ORDER property on the part instances to force single gates of a part onto the same packaged...
View Articlecan't use DRC "duplicate names across design"
Hii want to use DRC "duplicate names across design". in Capital Logic.open the project preferences and i found that rule item "duplicate names across design" is grey .i can't execute this rule check...
View ArticleRe: can't use DRC "duplicate names across design"
Hi Louis,I am not sure why it is grey, we are looking into that. However, if you right click on the DRC from within your Capital Logic project preferences you can change the status from "grey" (which...
View ArticleRe: VeSys 2.0 installation with McAfee
Hi, Are you running (or trying to run) VeSys 2.0 in the Evaluation mode? If true, then we have experienced some problems with some security software that still needs to learn that VeSys is safe, so we...
View ArticleHow to use variables in Calibre DRC Check Map statement
Hi all, I am very new to Calibre DRC deck creation.For experimentation purposes, I wish to write the statement like this : DRC Check Map myrule GDSII "Smylayer" "$mydtype" "$outputfile" APPEND...
View ArticleAutomation for: Creating Testpoint Summaryfile? / Wie testpointsummary Datei...
Hello,how to generate per automation-script the "Test-Point-Summary Reportfile", for an XPedition PCB-Design? (see picture) ----Hallo,kann ich irgendwie per Automation (vbs oder .net), automatisch die...
View ArticleRe: Automation for: Creating Testpoint Summaryfile? / Wie testpointsummary...
Hello Juergen,under Automation documents there is already a script (Expedition: TestPoint Report DOC-1939)Expedition: Testpoint Report Bortolo
View ArticleRe: How to get visible drill holes on layout?
You can try importing the gerbers and the drill files in a gerber viewer and print from there. You would print the layers overlapped with the drill. GC Prevue is free and can do the job.
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