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Re: Via simulation issue when translating from Allegro to Hyperlynx

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Not sure how it works in allegro but in Expedition PCB the pads are only removed when generating the gerbers/odb so they are also exported to the hyperlynx file.

But with hyperlynx 9.x you can toggle the removal of unused pads

 

 

MG581468:

 

HyperLynx v9.0 allows you to automatically remove the non-functional pads of all the vias in the design by selecting the Setup > Remove Non-Functional Pads menu pick.

 

 

When this command is invoked, all the pads will be removed EXCEPT the pads on the entry and exit layers and the pads on the outermost layers of the via (if different from the entry and exit layers of the via). The outermost layer pads are maintained to ensure the physical integrity of the signal via. This is a common practice in the manufacturing process.

 


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