Hello folks,
here a basic question that is driving us nuts about handling of hierarchical bus and partial bus.
Lets start with a simple example: You have a larger bus and would like to rip out two sub busses, half the bit-width of the first.
In the manual the suggestion is to use a sub bus with a rip net for busses.
So in a situation that demands that two hierarchical nets are connected to a hierarchical block the resulting design would be something like this:
In the first block called Matija1 we get the first half of the bus, and in the block Matija2 we get the second half of the block.
So far so good. All the checks and verifies like DRC-121 do not show any difficulties.
Let now copy this schematic another time. Now we have four blocks on two schematic pages on the same hierarchical level.
Same design same logic of exiting the bus.
A check and verify shows errors on DRC 12 for every single bus net starting form bus0 up to bus15, twice for every net.
drc-121 - [schematic: Schematic1, bus: bus(7:0)] Missing internal connection symbols on net 'bus0'
I have no logical explanation why this is an error.
But wait, there is more...
If I do not use the bus ripper function, but do rip separate signals one by one, then the single ripped signals are connected to the hierarchical block.
in picture the it looks like this.
Now I do NOT get any error for the single ripped signals, but only for the bus ripped ones. (Note the errors start with bus8, no errors for bus0 to bus7)
Can somebody help us find out why the tool is showing this as an error?
Many thanks
Matija