I had an occasion where insertion loss and return loss appeared swapped. They were not really, it just appeared that way. There was a problem in how my dc-blocking caps were routed on the board. My cap pads were on top of the vias (top layer). The green traces are on an internal layer. The pads and vias were physically connected so a fabricated board would work, but the little blue routes from the center of the cap pad to the center of the via were missing. So, Hyperlynx does not see a DC path from the cap pad to the via. Return loss will be 100 % reflection (0 dB) near 0 Hz, and very high insertion loss at low frequency. But Hyperlynx knew there was dielectric around them, so there is an ac path, so insertion loss is finite. This scenario matches your plots.
If this is your problem, I could not find a fix in Hyperlynx; the little blue traces have to be added in the board and the boards translated again.
