Jeff,
I have not done any work on creating custom DRC checks or scripts. I also have not received any additional information or example scripts that do custom DRC checks. Unfortunately, I don't really have the time to pursue anything like this (I'd probably hire an intern to do the work, if I had a starting point to give them). For now, what we've done is go through the entire set of DRC checks and decide which ones to enable and disable, how to set them each up for the best success, and how to deal with common failures. Still, the tool can report hundreds of errors/warnings that can safely be ignored, particularly on schematics with FPGAs and processors with lots of GPIO.
Here's a list of the Mentor Ideas that I've authored that have direct or indirect effects on DRC/Verify:
Add configuration for IODesigner to add no-connect and intrasheet symbols - D12517
Flag individual Verify/DRC warnings/errors for ignore - D7357
Enhance Verify to account for IODesigner Schematic Update Flow - D12518
Enhance DRC-106 and DRC-117 to ignore differential pairs
Enhancements to support DRC-117 for GPIO pins
Create an editor for verify_defaults.ini
Enhance DRC-108 to optionally ignore dangling nets - D8525
Enhance DRC-105 to ignore input pins connected only to analog pins - D8524
Enhance DRC-117 and -118 to recognize resistor arrays and networks - D8548