Let's start with the 15 mils: That's not a bad number to make sure the glass fibers and resin can build enough strength to resist delaminating. But consider tolerances. Add your vendors' feature location tolerance - 4 mils for a better vendor. Then there's the edge tolerance. Try another 4. Now you have to calculate how far the v-score cuts into your board - (1/2 thickness - 1/2 retention) - tan(1/2 score angle). To get that 15 mils, you need to set your design rule more like 35-40. And if you don't get to control which board vendors you use, increase the tolerances, purchasing is going to use the cheapest (as in least capable) vendor they can.
Now, how far away from the traces to run the copper? There is no common answer, it depends highly on yoru design. Unless the board is designed to be stripline on the layer in question, the location of the copper plane (current return path) has nothing to do with the traces on the layer with the plane. It's a function of the layer directly above or below. Signal currents want to use the shortest path for their return. If you end your layer 2 plane 2000 mils from the board edge, but have a signal on layer 1 that is 50 mils from the edge, you have increased the return path by at least 3900 mils. Now you have created a loop that can seriously degrade the integrity of the signal, radiate electromagnetic interference, create crosstalk.
Does this plane return high speed or RF currents (remember, currents can return on voltage planes)? Are you at risk of radiating these currents? Less "antenna" area is safer. Unless of course, it violates the concerns about microstrip return loops, explained above.
Once you have addressed all of those concerns and have decided it's simply a matter of how much copper, the goal is to keep the amount of copper on each layer as equal as possible to help the fab and assembly vendors avoid warping your board during processing.
So no one can give you the answer to "how far", unless they know your complete design requirements.