Hi!
After I assign models and nets to simulate I receive the following error, while I try to perform the DDR3 batch simulation.
The following devices have inconsistent "Net to IBIS Model/Selector" mappings.
All signals of the same type should share the same IBIS Model/Selector.
Typically, this indicates that a signal net was not categorized correctly.
Controller U10--
Signal_Type Pin# IBIS_Signal IBIS_Model/Selector Net_Name
DQS M38 IP_DDR_0_DQSp BCM28HPMFL3_T1XH_LPDDR3800M_CLK_DIFF_M38 CPU_DDR3_DQS0_P
DQS J38 IP_DDR_1_DQSp BCM28HPMFL3_T1XH_LPDDR3800M_CLK_DIFF_J38 CPU_DDR3_DQS1_P
DQS F38 IP_DDR_2_DQSp BCM28HPMFL3_T1XH_LPDDR3800M_CLK_DIFF_F38 CPU_DDR3_DQS2_P
DQS C38 IP_DDR_3_DQSp BCM28HPMFL3_T1XH_LPDDR3800M_CLK_DIFF_C38 CPU_DDR3_DQS3_P
DQS# M37 IP_DDR_0_DQSn BCM28HPMFL3_T1XH_LPDDR3800M_CLK_DIFF_M37 CPU_DDR3_DQS0_N
DQS# J37 IP_DDR_1_DQSn BCM28HPMFL3_T1XH_LPDDR3800M_CLK_DIFF_J37 CPU_DDR3_DQS1_N
DQS# F37 IP_DDR_2_DQSn BCM28HPMFL3_T1XH_LPDDR3800M_CLK_DIFF_F37 CPU_DDR3_DQS2_N
DQS# C37 IP_DDR_3_DQSn BCM28HPMFL3_T1XH_LPDDR3800M_CLK_DIFF_C37 CPU_DDR3_DQS3_N
DQ L36 IP_DDR_0_DQ0 GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D0
DQ L38 IP_DDR_0_DQ1 GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D1
DQ K33 IP_DDR_0_DQ2 GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D2
DQ K31 IP_DDR_0_DQ3 GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D3
DQ K34 IP_DDR_0_DQ4 GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D4
DQ J34 IP_DDR_0_DQ5 GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D5
DQ J31 IP_DDR_0_DQ6 GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D6
DQ J32 IP_DDR_0_DQ7 GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D7
DQ G34 IP_DDR_1_DQ2 GRPIDQ1_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D10
DQ G33 IP_DDR_1_DQ3 GRPIDQ1_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D11
DQ H36 IP_DDR_1_DQ4 GRPIDQ1_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D12
DQ F31 IP_DDR_1_DQ5 GRPIDQ1_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D13
DQ G30 IP_DDR_1_DQ6 GRPIDQ1_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D14
DQ G31 IP_DDR_1_DQ7 GRPIDQ1_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D15
DQ F32 IP_DDR_2_DQ0 GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D16
DQ E32 IP_DDR_2_DQ1 GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D17
DQ F35 IP_DDR_2_DQ2 GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D18
DQ E36 IP_DDR_2_DQ3 GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D19
DQ E33 IP_DDR_2_DQ4 GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D20
DQ E38 IP_DDR_2_DQ5 GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D21
DQ D30 IP_DDR_2_DQ6 GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D22
DQ D31 IP_DDR_2_DQ7 GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D23
DQ D34 IP_DDR_3_DQ0 GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D24
DQ C35 IP_DDR_3_DQ1 GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D25
DQ C34 IP_DDR_3_DQ2 GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D26
DQ C32 IP_DDR_3_DQ3 GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D27
DQ D33 IP_DDR_3_DQ4 GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D28
DQ B35 IP_DDR_3_DQ5 GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D29
DQ B38 IP_DDR_3_DQ6 GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D30
DQ B33 IP_DDR_3_DQ7 GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D31
DM J35 IP_DDR_0_DM GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_DQM0
DM H33 IP_DDR_1_DM GRPIDQ1_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_DQM1
DM F34 IP_DDR_2_DM GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_DQM2
DM B36 IP_DDR_3_DM GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_DQM3
What could be wrong here. Any help appreciated.
Regards,
M.