1. The HyperLynx Analog Simulation often throw out some strange error information.
2. The way that the xDX Designer introduce the error information is very bad. For example, there is not any special color or mark when the error information comes out. People must look carefully for the introduction information in a very long graph. People want get some hint just with one simple clicking on the screen to get the part or net.
3. It is very difficult to add some Probe point on the drawing. Absolutely, it will be better that to add probe point in the same way as the Pspice in orcad.
4. As the two files in attach, the HLA_DJD.ZIP will make the HyperLynx Analog Simulation throw some error information shown below:
include "resultDisplayFile.Aqr"
.include "..\..\genhdl\Schematic1\Schematic1.spi"
..\..\sym\s__zener_hv.spi(2): error -- s__zener_hv is a duplicate subcircuit element.
..\..\sym\s__zener_hv.spi(3): error -- VZ is a duplicate parameter.
..\..\sym\s__zener_hv.spi(4): error -- IR is a duplicate parameter.
..\..\sym\s__zener_hv.spi(5): error -- VR is a duplicate parameter.
..\..\sym\s__zener_hv.spi(6): error -- TCVZ is a duplicate parameter.
..\..\sym\s__zener_hv.spi(7): error -- IZK is a duplicate parameter.
..\..\sym\s__zener_hv.spi(8): error -- ZZK is a duplicate parameter.
..\..\sym\s__zener_hv.spi(9): error -- IZT is a duplicate parameter.
..\..\sym\s__zener_hv.spi(10): error -- ZZT is a duplicate parameter.
..\..\sym\s__zener_hv.spi(11): error -- CZ is a duplicate parameter.
..\..\sym\s__zener_hv.spi(15): error -- the name vt appears twice in subckt .
..\..\sym\s__zener_hv.spi(16): error -- the name isd appears twice in subckt .
..\..\sym\s__zener_hv.spi(17): error -- the name r2 appears twice in subckt .
..\..\sym\s__zener_hv.spi(18): error -- the name nz appears twice in subckt .
..\..\sym\s__zener_hv.spi(19): error -- the name tcr1 appears twice in subckt .
..\..\sym\s__zener_hv.spi(20): error -- the name r1 appears twice in subckt .
..\..\sym\s__zener_hv.spi(21): error -- the name rz appears twice in subckt .
..\..\sym\s__zener_hv.spi(22): error -- the name v1 appears twice in subckt .
..\..\sym\s__zener_hv.spi(23): error -- D2 is a duplicate diode element .
..\..\sym\s__zener_hv.spi(24): error -- D3 is a duplicate diode element .
..\..\sym\s__zener_hv.spi(25): error -- R1 is a duplicate resistor element.
..\..\sym\s__zener_hv.spi(26): error -- E1 is a duplicate voltage-controlled voltage source element.
..\..\sym\s__zener_hv.spi(28): error -- I1 is a duplicate independent current source element.
..\..\sym\s__zener_hv.spi(29): error -- R2 is a duplicate resistor element.
..\..\sym\s__zener_hv.spi(30): error -- dm is a duplicate model.
..\..\sym\s__zener_hv.spi(36): error -- dl is a duplicate model.
.option tnom=27
.option dcmode=all gmin=1e-12 nodeset=1
.option trmode=fast
.option method=trap
******end of additional commands*******
.end
After the "D2" was deleted, the error information is disappearing. But as you know, D2 and D5 are all come from the library located in the director which path is \SDD_HOME\standard\templates\hyperlynx analog\Central Library\HLASym_CentralLibrary .
If the D5 is deleted, the error information is also disappearing, but new error information such as "no convergence in transient analysis" will shown out, just as the HLA_DJD_2.ZIP.
The error information from HLA_DJD_2.ZIP is shown below:
n1n797 last converged value = 0.904141 new value = 0.91401
out- last converged value = 1.11178 new value = 1.14664
no convergence in xd1.
C:\MentorGraphics\EEVX.1.2\SDD_HOME\dxsim\win64\bin\vbase.exe: error -- no convergence in transient analysis at time 0.400034.
If the R7 is changed to 1M, it's ok!
Other，Sometimespause a few minutes in places shown below.
I want to know what make these thing happen and how to avoid them. It is very difficult to use the HyperLynx Analog Simulation. So many time are wasted on killing these strange thing .
Thank you!