Modeling package and on-chip capacitors for Decoupling Analysis

Hi,

I am trying to use Hyperlynx PI (ver. 9.3) to do decoupling analysis for Xilinx Virtex6 and Kintex7 fpgas. The user guides of these FPGAs explicitly mention that these FPGAs have enough on-package decoupling capacitors that we don't need to add any further ceramic capacitors on PCB to bring down the impedance for mid - high frequencies. Kintex-7 even provides the values of these on-package decaps (C, ESL, and ESR).

How can I feed these inputs into Hyperlynx PI while doing decoupling analysis. I want to model these along with xilinx's recommended bulk capacitor and VRM model to check the impedance profile.

In addition, how can we input the package inductance of these fpgas?

Regards,

Binayak.