Hi Vern, thanks so much for your reply. It seems that indeed it's complicated and I will take some time to get this figured out, so I'll leave it for after-tapeout mode. I'll come back here to comment on what I find (unfortunately I am a PhD student so I have no posting rights in SupportNet )
I am wondering though how this issue is handled in real world designs. I find it hard to believe that verification people just make amends with the idea of having all the parasitics tied to the same node when simulating chips with multiple power domains!!!
Cheers,
Jorge.