Hi Oscar--
To address TI's statements:
>>the DDR wizard makes many assumptions
Yes, the DDR Wizard does make assumptions, but all of them are extremely reasonable. For instance, we assume that I/O buffers get modeled as I/O models...
>>is incompatible with many different IBIS model formats
This sounds to me like they made an unusual choice with how they modeled their I/Os and don't feel like changing their models. The DQS and DQ pins on a DDR controller are I/Os - they drive in both directions. So, I'm not sure why anyone would model them using separate buffers, especially if they expected their customers to do system-level simulations with the models.
>>It also assumes the model to model relative timing is accurate, but this is not a general requirement for IBIS
It is true that IBIS does not require different models to have time-correlated V-t curves (only the V-t curves within a single model need to be time-correlated). However, the signals with the tightest timing margins are the DQ and DQS signals, which always use the same buffers and therefore the same models (I have yet to see a part where this was not the case). But even for signals that do use different models, we have a V-t stripping algorithm that will align edges as they start transitioning (default threshold is 1% - and can be changed under Setup -> Options -> General -> Advanced).
--Pat