Hi Pat,
thank you for your answer.
Could you please help me to understand better hyperlynx weak points below (from TI's BLOG):
Unfortunately the DDR wizard makes many assumptions and is incompatible with many different IBIS model formats.
For example the wizard requires that the data and other IO models are modeled as IO and cannot handle discrete selectors with separate input and output models. This is a major issue since TI generally includes separate input and output models rather than IO models.
It also assumes the model to model relative timing is accurate, but this is not a general requirement for IBIS since IBIS is only designed really for signal integrity and not pin to pin timing checks.
Is this really the case?
Kind Regards,
Oscar