Hello! I'm a newbie to Calibre nmLVS. In the layout of my cell, I made a custom plate capacitance with 2 metal layers. This capacitance is between an internal node (b) and the output pin (out). In my schematic, I put a "cap" from analogLib to represent this capacitance, but when I run LVS it fails (because it sees the cap in the source, but not a corresponding instance in layout).
Do you know how I can have a positive check with LVS? I tried by changing "cap" to "pcapacitor" hoping that LVS would ignore that, but I have the same error.
Thank you very much!
