Your transient simulation time depends on the the settling time of your PLL circuit. You can look up how to calculate a PLL settling time. This will be a decent estimate, as your actual simulation result (with full transistor models) will vary. Set your ending simulation time for something larger than this estimate.
You can and should perform some sort of corner or M-C simulation to see where your performance extremes may be. Depending on who you consult, some engineers prefer all-corner simulations while other prefer random corner or Monte-Carlo. My personal take is that you need a combination of both. That is, you should select and simulate your extreme process corners (WCP, WCS, WC0, WC1, TYP) with associated power and temperature extremes. This will give you one set of data. You can also set up a Monte-Carlo scenario where you randomize the process/power/temp variables and get more coverage in your simulation space. With these data sets combined, you should be able to get a good feel for your circuit's performance.
Hope this is helpful.