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Re: Error on generation of Cadence Allegro 15.Xx netlist generated from DX designer

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It won't generate any outputs whilst you have errors in the schematic, you need to correct all errors before you can proceed. Looking at the errors the bad name error is due to the symbol name being 2INDDIO-B.n1 you can only have numbers after the decimal point as in 2INDDIO-B.1 etc.

It also looks like one error is caused because you have a space in the name of a component TIE BAR.

Not sure on the Hetero error, but it might be because you have pin swaps across devices.


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